AD9879 View Datasheet(PDF) - Analog Devices
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AD9879 Datasheet PDF : 32 Pages
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When this bit is set default low, the AD9879 serial port is in
MSB-first format. In MSB-first mode, the instruction byte and
data bytes must be written from the MSB to the LSB. In MSB-
first mode, the serial port internal byte address generator
decrements for each byte of the multibyte communication cycle.
When incrementing from 0x1F, the address generator changes
to 0x00. When decrementing from 0x00, the address generator
changes to 0x1F.
NOTES ON SERIAL PORT OPERATION
The AD9879 serial port configuration bits reside in Bits 6 and 7
of Register 0x00. It is important to note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register may occur
during the middle of the communication cycle. Care must be
taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
R/W N1 N0 A4 A3 A2 A1 A0 D7n D6n
D7n D6n
D20 D10 D00
D20 D10 D00
Figure 10. Serial Register Interface Timing MSB First
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D00 D10 D20
D6n D7n
D6n D7n
Figure 11. Serial Register Interface Timing LSB First
AD9879
The same considerations apply to setting the reset bit in
Register 0x00. All other registers are set to their default values,
but the software reset does not affect the bits in Register 0x00.
It is recommended to use only single-byte transfers when
changing serial port configurations or initiating a software
reset.
A write to Bits 1, 2, and 3 of Register 0x00 with the same logic
levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows
the user to reprogram a lost serial port configuration and to
reset the registers to their default values.
A second write to Register 0x00 with the reset bit low and the
serial port configuration as specified above (XY) reprograms
the OSCIN multiplier setting. A changed fSYSCLK frequency is
stable after a maximum of 200 fMCLK cycles (wake-up time).
CS
SCLK
SDIO
tDS
tSCLK
tPWH
tPWL
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 12. Timing Diagram for Register Write to AD9879
CS
SCLK
SDIO
SDO
DATA BIT N
tDV
DATA BIT N – 1
Figure 13. Timing Diagram for Register Read
Rev. A | Page 21 of 32
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