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AD9876 View Datasheet(PDF) - Analog Devices

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AD9876 Datasheet PDF : 24 Pages
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AD9876
the first address to be accessed. The AD9876 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Figures 10a and 10b show how the serial port words are built
for each of these modes.
SENABLE
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDATA
R/W I6(N) I5(N) I4 I3 I2 I1 I0 D7N D6N
D20 D10 D00
Figure 10a. Serial Register Interface Timing MSB-First
SENABLE
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDATA
I0 I1 I2 I3 I4 I5(N) I6(N) R/W D00 D10 D20
D6N D7N
Figure 10b. Serial Register Interface Timing LSB-First
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all
registers except Register 0 are set to their default values. Regis-
ter 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
Address
(hex)
0
1
2
3
4
5
6
7
8
F
Table IV. Register Layout
Bit 7
Power-
Down
Regulator
Power-
Down
Regulator
Tx Port
Negative
Edge
Sampling
Rx Port
Negative
Edge
Sampling
Invert
CLK-B
Bit 6
SPI
LSB First
Power-
Down
PLL-B
Power-
Down
PLL-B
ADC Clock
Source
PLL-B/2
Bit 5
Software
Reset
Power-
Down
PLL-A
Bit 4
Power-
Down
DAC
Power-
Down
PLL-A
Power-
Down
DAC
PLL-B
(×M) Multiplier
<5:4>
Bit 3
Bit 2
Power-
Down
Interpolator
Power-
Down
Rx
Reference
Power-
Down
Interpolator
Power-
Down
Rx
Reference
PLL-B
(րN) Divider
<3:3>
Bit 1
Bit 0
Power- Power-
Down Down
ADC and Rx LPF and
FPGA CPGA
Power- Power-
Down Down
ADC and Rx LPF and
FPGA CPGA
PLL-A
(×M) Multiplier
<1:0>
Default
(hex)
0 × 00
Comments
Read/Write
0 × 00
Read/Write
PWR DN
Pin Low
0 × 9F
Read/Write
PWR DN
Pin High
0 × 02 Read/Write
Rx LPF
Rx Path Rx Digital Fast ADC
Tuning
DC Offset HPF
Sampling
In Progress Correction Bypass
(Read-Only)
Wideband
Rx LPF
Enable
1-Pole
Rx LPF
Rx LPF fc Adjust <7:0>
PGA
Gain Set
by Register
Rx Path Gain Adjust <4:0>
Interpolation Filter Select
<3:0>
Power-Down
Interpolator
at
Tx QUIET
Pin Low
Tx Port
LS Nibble
First
Invert
CLK-A
Disable
CLK-B
Disable
CLK-A
Three-State Rx Port
Rx Port
LS Nibble
First
Die Revision Number <3:0>
Rx LPF
Bypass
0 × 01
0 × 80
0 × 00
Tx Port
0 × 00
Demultiplexer
Bypass
Rx Port
Multiplexer
Bypass
0 × 00
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read- Only
–20–
REV. A
 

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