AD9868 View Datasheet(PDF) - Analog Devices
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AD9868 Datasheet PDF : 36 Pages
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AD9868
A hardware reset (RESET pin) or software reset (Bit 5 of
Register 0x00) can be used to place the AD9868 into a known
state of operation as determined by the state of the MODE and
CONFIG pins. A dc offset calibration and filter tuning routine
is also initiated upon a hardware reset, but not with a software
reset. Neither reset method flushes the digital interpolation filters
in the Tx path. Refer to the Half-Duplex Mode and Full-Duplex
Mode sections for information on flushing the digital filters.
A hardware reset can be triggered by pulsing the RESET pin low
for a minimum of 50 ns. The SPI registers are instantly reset to
their default settings upon RESET going low, whereas the dc offset
calibration and filter-tuning routine is initiated upon RESET
returning high. To ensure sufficient power-on time of the various
functional blocks, RESET returning high should occur no less
than 10 ms upon power-up. If a digital reset signal from a
microprocessor reset circuit (such as ADM1818) is not available,
a simple R-C network referenced to DVDD can be used to hold
RESET low for approximately 10 ms upon power-up.
ANALOG AND DIGITAL LOOPBACK TEST MODES
The AD9868 features analog and digital loopback capabilities
that can assist in system debug and final test. Analog loopback
routes the digital output of the ADC back into the Tx data
path prior to the interpolation filters such that the Rx input
signal can be monitored at the output of the TxDAC or IAMP.
As a result, the analog loopback feature can be used for a half-
duplex or full-duplex interface to allow testing of the functionality
of the entire IC (excluding the digital data interface).
For example, the user can configure the AD9868 with similar
settings as the target system, inject an input signal (sinusoidal
waveform) into the Rx input, and monitor the quality of the
reconstructed output from the TxDAC or IAMP to ensure a
minimum level of performance. In this test, the user can exercise
the RxPGA as well as validate the attenuation characteristics of
the RxLPF. Note that the RxPGA gain setting should be selected
such that the input does not result in clipping of the ADC.
Digital loopback can be used to test the full-duplex digital
interface of the AD9868. In this test, data appearing on the
Tx[5:0] port is routed back to the Rx[5:0] port, thereby
confirming proper bus operation. The Rx port can also be
three-stated for half-duplex and full-duplex interfaces.
Table 26. SPI Registers for Test Modes
Address (Hex)
Bit Description
0x0D
7
Analog loopback.
6
Digital loopback.
5
Rx port three-state.
Rev. 0 | Page 34 of 36
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