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AD9777 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9777 Datasheet PDF : 60 Pages
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AD9777
LECROY
PULSE
TRIG
GENERATOR INP
SIGNAL GENERATOR
INPUT CLOCK
DATACLK
CLK+/CLK–
AWG2021
OR
DG2020
40-PIN RIBBON CABLE
DAC1, DB15–DB0
DAC2, DB15–DB0
AD9777
JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON
SOLDERED/IN
JP1 –
×
JP2 –
JP3 –
×
JP5 –
×
JP6 –
JP12 –
JP24 –
JP25 –
×
JP26 –
×
JP27 –
JP31 –
JP32 –
JP33 –
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND
JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53,
JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO PORT DATA INPUT MODE SECTION
FOR MORE INFORMATION.
Figure 101. Test Configuration for AD9777 in Two-Port Mode with PLL Enabled Signal Generator Frequency = Input Data Rate,
DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
LECROY
PULSE
TRIG
GENERATOR INP
SIGNAL GENERATOR
INPUT CLOCK
AWG2021
OR
DG2020
ONEPORTCLK CLK+/CLK–
DAC1, DB15–DB0
DAC2, DB15–DB0 AD9777
JUMPER CONFIGURATION FOR ONE PORT MODE PLL ON
SOLDERED/IN
JP1 –
×
JP2 –
JP3 –
×
JP5 –
JP6 –
JP12 –
JP24 –
JP25 –
×
JP26 –
JP27 –
×
JP31 –
×
JP32 –
JP33 –
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
Figure 102. Test Configuration for AD9777 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,
ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
Rev. C | Page 49 of 60
 

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