AD9713BAN View Datasheet(PDF) - Fairchild Semiconductor

Part Name

Description

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AD9713BAN

EVALUATION BOARD

Fairchild Semiconductor 

Table 5: Timing Specification

Function Description

Min Typ Max Unit

tpd1

tdp2

tdp3

tdp4

ts

th

tpwH

tpwL

tpwH

tpwL

SPT7820/24, CLK

to Data Valid Prop

Delay

- 14 18 nsec

MAX9686 Prop.

Delay

-

6

9 nsec

SPT7820/24, T(fall)

Prop. Delay

4.5

7 10 nsec

74F174, Prop.

Delay

4.5

7 10 nsec

74F174 Setup Time

4

-

- nsec

74174, Hold Time

4

-

- nsec

CLK Positive Pulse

Width (SPT7820)

20

- 300 nsec

CLK Negative Pulse

Width (SPT7820)

20

-

- nsec

CLK Positive Pulse

width (SPT7824)

10

- 300 nsec

CLK Negative pulse

Width (SPT7824)

10

-

- nsec

SPT7820/24 ACQUISITION TIME SPECIFICATION

Figure 8: Acquisition Time

+ 2V

ANALOG

INPUT

- 2V

Vin Hold time

(5 ns min)

CLOCK

INPUT

50%

INTERNAL

THA TIMING

+ FS

INTERNAL

THA OUTPUT

- FS

TRACK

Tacq 1

TpwH

HOLD

Settle to 1/2 LSB

TRACK

Tacq 2

The acquisition time (Tacq) is defined as the hold to track full

scale settling time for the internal track-and-hold (THA). Logic

low of the clock input corresponds to track mode and logic

high is the hold mode for the internal THA. Figure 8 shows two

types of acquisition time:

1) Tacq 1 is the settling time of the THA when it is in track

and it is driven by the analog input switching.

2) Tacq 2 is the amount of time it takes for the internal

THA of the ADC to reacquire the analog input when

switching from hold to track (CLK IN from high to low)

to within 1/2 LSB.

Both Tacq 1 and Tacq 2 need the same amount of time (see

the acquisition time specification in the respective data sheet).

The low-to-high clock transition should be placed after both

the analog input and internal THA are settled. The analog

input must remain for at least 5 ns (Vin hold time) after the low

to high clock transition. Keep the clock positive pulse width

(TpwH) to within the recommended limit. (Refer to the speci-

fication in the respective data sheet.)

TIMING CONSIDERATIONS WHEN USING AN

EXTERNAL TRACK-AND-HOLD

The signal-to-noise ratio (SNR) and the total harmonic distor-

tion (THD) degrade as the analog input frequency increases.

These parameters imply that the differential linearity error

(DLE) and the integral linearity error (ILE) degrades as well

at high frequency. This degradation is mainly due to aperture

jitter and/or analog input bandwidth limitation and/or slew rate

limitation of the SPT7820 and SPT7824. Below 1 MHz, the

SNR and THD of the SPT7820 and SPT7824 are generally

constant. In order to bring these accuracies up (at high

frequency), you may need to buffer the analog input using a

track-and-hold amplifier (THA). THAs can be imperfect (es-

pecially at high frequency); otherwise, the dynamic perfor-

mance of the SPT7820 or SPT7824 would be constant and

equal to its performance at 1 MHz.

Selecting an acceptable THA for a specific application is

sometimes difficult. The timing diagram shown in figure 9 and

table 6 illustrate the critical timing necessary when driving the

ADC from a THA.

Figure 9-Critical Timing Between External THA and ADC

th1

Aperture delay

THA IN

tTHS

THA OUT

THA

DIFF CLK

tHTS

TRACK

HOLD

ADC

CLK

ADC

OUT

tpd1

Valid Data

Pedestal

tHTS

(THA tacq )

tacq

(ADC)

Valid Data

Droop

AN7820/24

6

5/22/97

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