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AD9713JN View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9713JN
ADI
Analog Devices ADI
AD9713JN Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
- RNRLOGDEVICES fRK-ON-DEHRND HOTLINE
Page 25
AD9712/AD9713
Parameter (Conditious)
Test AD97UJNIjP
Temp Level MiD Typ Max
AD9713JNIjP
MiD Typ Mu. Units
DIGITAL INPUTS
Logic "I" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitallce
Input SetUp Time (t8)12
Input Hold Time (tiVU
Latch Pulse Width (tLPW)
(Transparent)
Full VI
-1.0 -0.8
2.0
Full VI
-1.7 -1.5
Full VI
20
Full VI
10
+ 25°C V
3
3
+ 25°C V
3
3
+ 25"C V
3
3
+25"C V
2.5
4
V
0.8 V
20
600 f.LA
pF
fiS
fiS
ns
AC LINEARITY1.
Spurious-Free Dynamic Range
+25°C V
-60
-55
dBc
POWER SUPPL ylS
Positive Supply Current (+5.0 V) +2S"C I
Full VI
10
20
mA
23
mA
OBSOLETE Negative Supply Current (-5.2 V)
Nominal Power Dissipation
Power Supply
Rejection Ratio (PSRR)16
+ 25"C I
Full VI
+25"C V
+25°C I
130 160
170
676
50
350
135 165 mA
175 mA
726
mW
50
350 IJ.AN
NOTES
'AbsolUte maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired.
Functioual operability is DOtnco:ssarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2"fypicaI thcrmal impedances: 28-pin plastic DIP 8J/\ = 4row; 8JC = 7"CIW; 28-pin PLCC 9,/\ = 48°C/Wj 8Jc = IOOCJW.
3Measured as error of me ratio of full-scale current to current throush RSET (160 IJ.Anominal); ratio is nominally 128.
4Pu11-scale variattous &moor devices are more severe when driving REFERENCE IN directly.
'Frequ~ at which a 3 dB reduction in output of DAC is observed; RL = 50 OJ 50% modulation at midscale.
6Based on Ips = 128 (V~)
when using internal amplifier.
70utpUt settJin& to 0.1%.
'Measured at midscale transition, (0 :to.O24%.
'Measured from falling edge of LATCH ENABLE signal to 50% point of full.scale transition.
"'Glitch impuJlie combines me absolute value of positive and negarive transitions operating in latched mode.
uMcasurcd wim RL = SO 0 and DAC operating in latched mode.
"Data must remain stable prior (0 falling edge of LATCH ENABLE signal for specified time.
13Data must remain stable after rising edge of LATCH ENABLE signal for specified time.
= 14Update rate s50 MSPS; output frequency
5 MHz.
"Supply voltages should remain stable within :t5% for normal operation.
16Mcasured
It :t5% of + V s (AD9713
- only) and V s (AD9712
or AD9713)
using external reference.
Specifications subject to chance withoUt ponce.
EXPLANATION OF TEST LEVELS
Level
- I - 100% production tested.
II 100% production tested at + 25°C. and sample tested at
specifiedtemperatures.
III - Sampletested only.
IV - Parameteris guaranteedby design and
characterizationtesting.
- V Parameter is a typical value only.
- VI All devices arc 100% production tested at +25°C. 100%
production tested at temperatUre extremes for extended
temperature devices; sample tested at temperature
exttcmes for commercial/industrial devices.
ORDERING GUIDE
Model
AD9712JN
AD9712JP
AD97I3JN
AD9713JP
Description
ECL-Compatible Plastic DIP
ECL-Compatible PLCC
ITL-Compatible Plastic DIP
ITL-Compatib1e PLCC
= *N = Plastic DIP; P Plastic Leaded Chip Carrier.
Package
Option.
N-28
P-28A
N-28
P-28A
REV. A
-3-
 

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