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AD9696TZ/883B View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9696TZ/883B
ADI
Analog Devices ADI
AD9696TZ/883B Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AD9696/AD9698
PIN CONFIGURATIONS
Name
Q1OUT
Q1OUT
GROUND
LATCH
ENABLE 1
N/C
–VS
–IN1
+IN1
+IN2
–IN2
+VS
LATCH
ENABLE 2
Q2OUT
Q2OUT
Q1OUT (N/C) 1
Q1OUT (–VS) 2
16 Q2OUT (LATCH ENABLE 1)
15 Q2OUT (GROUND)
GROUND (–IN1) 3
LATCH ENABLE 1 (+IN1) 4
N/C (+IN2) 5
–VS (–IN2) 6
14 GROUND (Q1OUT)
TOP VIEW
(Not to Scale)
13 LATCH ENABLE 2 (Q1OUT)
12 N/C (Q2OUT)
11 +VS (Q2OUT)
–IN1 (+VS) 7
+IN1 (N/C) 8
10 –IN2 (GROUND)
9 +IN2 (LATCH ENABLE 2)
+VS 1
8 QOUT
+IN 2
–IN 3
–VS 4
TOP VIEW
(Not to Scale)
7 QOUT
6 GROUND
5 LATCH
ENABLE
AD9698KN/KQ/TQ
[AD9698KR/TZ PINOUTS SHOWN IN ( )]
AD9696KN/KR/KQ/TQ/TZ
Function
One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at +IN1 is greater than voltage at
–IN1 and LATCH ENABLE 1 is at logic LOW.
One of two complementary outputs. Q1OUT will be at logic HIGH if voltage at –IN1 is greater than voltage at
+IN1 and LATCH ENABLE 1 is at logic LOW.
Analog and digital ground return. All GROUND pins should be connected together and to a low impedance
ground plane near the comparator.
Output at Q1OUT will track differential changes at the inputs when LATCH ENABLE 1 is at logic LOW.
When LATCH ENABLE 1 is at logic HIGH, the output at Q1OUT will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns.
No internal connection to comparator.
Negative power supply connection; nominally –5.2 V.
Inverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #1.
Noninverting input of differential input stage for Comparator #2.
Inverting input of differential input stage for Comparator #2.
Positive power supply connection; nominally +5 V.
Output at Q2OUT will track differential changes at the inputs when LATCH ENABLE 2 is at logic LOW.
When LATCH ENABLE 2 is at logic HIGH, the output at Q2OUT will reflect the input state at the application of
the latch command, delayed by the Latch Enable Setup Time (tS). Since the architecture of the input stage (see
block diagram) is faster than the logic of the latch stage, data will typically be latched if applied to the comparator(s)
within 1.7 ns after the latch. This is the Setup Time (tS); for guaranteed performance, tS must be 3 ns.
One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at –IN2 is greater than voltage at
+IN2 and LATCH ENABLE 2 is at logic LOW.
One of two complementary outputs. Q2OUT will be at logic HIGH if voltage at +IN2 is greater than voltage at
–IN2 and LATCH ENABLE 2 is at logic LOW.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
 

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