AD9683BCPZ-250 View Datasheet(PDF) - Analog Devices
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AD9683BCPZ-250 Datasheet PDF : 44 Pages
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Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
tSPI_RST
AD9683
Test Conditions/Comments
See Figure 67
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
Time required after hard or soft reset until SPI access is available
(not shown in figures)
Min Typ Max Unit
2
ns
2
ns
40
ns
2
ns
2
ns
10
ns
10
ns
10
ns
10
ns
500
µs
Timing Diagrams
ANALOG
INPUT
SIGNAL
N – 36
N – 35
N – 34
N – 33
SAMPLE N
N+1
N–1
CLK–
CLK+
CLK–
CLK+
SERDOUT0±
RFCLK
CLK–
CLK+ tREFS
SYSREF+
SYSREF–
SAMPLE N – 36
ENCODED INTO 2
8B/10B SYMBOLS
SAMPLE N – 35
ENCODED INTO 2
8B/10B SYMBOLS
Figure 2. Data Output Timing
SAMPLE N – 34
ENCODED INTO 2
8B/10B SYMBOLS
tREFH
tREFSRF
tREFHRF
Figure 3. SYSREF± Setup and Hold Timing (Clock Input Either RFCLK or CLK±, Not Both)
Rev. 0 | Page 9 of 44
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