AD9683BCPZ-170 View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

AD9683BCPZ-170

14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

Analog Devices 

AD9683

Data Sheet

Parameter1

TWO-TONE SFDR

fIN1 = 184.12 MHz (−7 dBFS), fIN2 = 187.12 MHz (−7 dBFS)

FULL POWER BANDWIDTH2

Temperature

25°C

25°C

AD9683-170

AD9683-250

Min Typ Max Min Typ Max

87

1000

87

1000

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions.

2 Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.

Unit

dBc

MHz

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p

full-scale input range, DCS enabled, default SPI, unless otherwise noted.

Table 3.

Parameter

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Input CLK± Clock Rate

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Input Resistance

RF CLOCK INPUT (RFCLK)

RF Clock Rate

Logic Compliance

Internal Bias

Input Voltage Range

High Input Voltage Level

Low Input Voltage Level

High Level Input Current

Low Level Input Current

Input Capacitance

Input Resistance (AC-Coupled)

SYNCIN INPUTS (SYNCINB+/SYNCINB−)

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage Range

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Input Resistance

Temperature

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Min

Typ

Max

40

0.3

AGND

0.9

0

−60

8

625

CMOS/LVDS/LVPECL

0.9

3.6

AVDD

1.4

+60

0

4

10

12

625

AGND

1.2

AGND

0

−150

8

1500

CMOS/LVDS/LVPECL

0.9

AVDD

AVDD

0.6

+150

0

1

10

12

0.3

DGND

0.9

−5

−10

12

CMOS/LVDS

0.9

1

16

3.6

DVDD

1.4

+5

+10

20

Unit

MHz

V

V p-p

V

V

µA

µA

pF

kΩ

MHz

V

V

V

V

µA

µA

pF

kΩ

V

V p-p

V

V

µA

µA

pF

kΩ

Rev. 0 | Page 6 of 44

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