datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

AD9609BCPZRL7-65 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9609BCPZRL7-65 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9609
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max Unit
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
10
ns
output relative to the SCLK falling edge
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
10
ns
input relative to the SCLK rising edge
Rev. 0 | Page 8 of 32
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]