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AD9609 Просмотр технического описания (PDF) - Analog Devices

Номер в каталогеКомпоненты Описаниепроизводитель
AD9609 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter ADI
Analog Devices ADI
AD9609 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9609
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
AD9609-20/AD9609-40
Temp Min Typ
Max
AD9609-65
AD9609-80
Min Typ Max Min Typ Max Unit
Full
625
625
625 MHz
Full 3
20/40 3
65 3
80 MSPS
Full 50/25
15.38
12.5
ns
25.0/12.5
7.69
6.25
ns
Full
1.0
1.0
1.0
ns
Full
0.1
0.1
0.1
ps rms
Full
3
Full
3
Full
0.1
Full
8
Full
350
Full
600/400
Full
2
3
3
ns
3
3
ns
0.1
0.1
ns
8
8
Cycles
350
350
μs
300
260
ns
2
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
VIN
CLK+
CLK–
DCO
DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
N–8
N–7
N–6
tPD
Figure 2. CMOS Output Data Timing
N–5
N–4
Rev. 0 | Page 7 of 32
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