AD9609 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9609

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

AD9609

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

USR2 (Register 0x101)

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode

rates below about 5 MSPS. When a low encode rate is detected,

an internal oscillator, GCLK, is enabled ensuring the proper

operation of several circuits. If set low, the detector is disabled.

Bit 2—Run GCLK

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

Bit 0—Disable SDIO Pull-Down

This bit can be set high to disable the internal 30 kΩ pull-down

on the SDIO pin, which can be used to limit the loading when

many devices are connected to the SPI bus.

Rev. 0 | Page 30 of 32

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