AD9609 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD9609 Datasheet PDF : 32 Pages
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AD9609
Addr
(Hex)
0x0E
Register Name
BIST enable
Bit 7
(MSB)
Open
Bit 6 Bit 5
Open Open
Bit 4
Open
Bit 3
Open
Bit 2
BIST
INIT
Bit 1
Open
Bit 0
(LSB)
BIST enable
Default
Value
(Hex)
0x00
0x10 Offset adjust
0x14 Output mode
0x15 Output adjust
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Open
Output
disable
Open Output
invert
00 = offset binary
01 = twos complement
10 = gray code
11 = offset binary
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
11 = 4 stripes
3.3 V data
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
0x00
0x00
0x22
0x16
0x17
0x18
0x19
Output phase
Output delay
VREF
USER_PATT1_LSB
DCO
Output
polarity
0=
normal
1=
inverted
Open Open
Open
Open
Enable
DCO
delay
Open Enable
data
delay
Open
Reserved =11
B7
B6
Internal VREF adjustment,
Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.60 V p-p
100 = 2.0 V p-p
B5
B4
B3
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
Open
B2
B1
B0
0x00
0x00
0xE0
0x00
0x1A USER_PATT1_MSB B15
B14 B13
B12
B11
B10
B9
B8
0x00
0x1B USER_PATT2_LSB B7
B6
B5
B4
B3
B2
B1
B0
0x00
0x1C USER_PATT2_MSB B15
B14 B13
B12
B11
B10
B9
B8
0x00
0x24 BIST signature LSB
BIST signature, Bits[7:0]
0x00
0x2A OR/MODE select Open
Open Open
Open
Open
Open
Open
0 = MODE
1 = OR
(default)
0x01
1.1. AD9609-Specific Customer SPI Control
0x101
USR2
1
Open
Enable Run
GCLK GCLK
detect
Rev. 0 | Page 29 of 32
Open
Disable SDIO
pull-down
0x88
Comments
When Bit 0 is set,
the built in self-test
function is initiated.
Device offset trim
Configures the
outputs and the
format of the data
Determines CMOS
output drive
strength properties
On devices that
utilize global clock
divide, determines
which phase of the
divider output is
used to supply the
output clock;
internal latching is
unaffected
Sets the fine output
delay of the output
clock but does not
change internal
timing
Selects and/or
adjusts the VREF
full-scale span
User-defined
pattern, 1 LSB
User-defined
pattern, 1 MSB
User-defined
pattern, 2 LSB
User-defined
pattern, 2 MSB
Least significant
byte of BIST
signature, read only
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or OR
(output) on external
Pin 23
Enables internal
oscillator for clock
rates <5 MHz
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