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AD9609 View Datasheet(PDF) - Analog Devices

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AD9609 Datasheet PDF : 32 Pages
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AD9609
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17.
Addr
(Hex) Register Name
Chip Configuration Registers
0x00 SPI port
configuration
Bit 7
(MSB)
0
Bit 6 Bit 5
LSB Soft
first reset
Bit 4
1
Bit 3 Bit 2
1
Soft
reset
Bit 1
Bit 0
(LSB)
LSB
0
first
0x01 Chip ID
0x02 Chip grade
Open
Device Index and Transfer Register
0xFF Transfer
Open
8-bit chip ID, Bits[7:0]
AD9609 = 0x71
Speed grade ID, Bits[6:4]
(identify device variants of
chip ID)
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Open Open Open Open Open
Open
Open Transfer
Program Registers
0x08 Modes
0x09 Clock
0x0B Clock divide
0x0D Test mode
External
Pin 23
mode
input
enable
Open
External Pin 23
function when
high
00 = full power
down
01 = standby
10 = normal
mode: output
disabled
11 = normal
mode: output
enabled
Open Open
Open
Open
Open
User test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
Reset
PN
long
gen
Reset
PN
short
gen
Open Open
00 = chip run
01 = full power-down
10 = standby
11 = chip wide digital
reset
Open Duty cycle
stabilize
Clock divider, Bits[2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Default
Value
(Hex)
Comments
0x18
Read only
Read only
The nibbles are
mirrored so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode
Unique chip ID used
to differentiate
devices; read only
Unique speed grade
ID used to
differentiate
devices; read only
0x00
0x00
Synchronously
transfers data from
the master shift
register to the slave
Determines various
generic modes of
chip operation
0x01
0x00
Enable internal duty
cycle stabilizer (DCS)
The divide ratio is
the value plus 1
0x00
When set, the test
data is placed on
the output pins in
place of normal
data
Rev. 0 | Page 28 of 32
 

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