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AD9609 Просмотр технического описания (PDF) - Analog Devices

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AD9609 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter ADI
Analog Devices ADI
AD9609 Datasheet PDF : 32 Pages
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AD9609
VOLTAGE REFERENCE
0
A stable and accurate 1.0 V voltage reference is built into the
–0.5
AD9609. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
–1.0
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
–1.5
practices for PCB layout of VREF.
INTERNAL VREF = 0.996V
Internal Reference Connection
–2.0
A comparator within the AD9609 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
VIN+
VIN–
–2.5
–3.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LOAD CURRENT (mA)
Figure 43. VREF Accuracy vs. Load Current
External Reference Operation
1.0µF
VREF
0.1µF
SENSE
ADC
CORE
SELECT
LOGIC
0.5V
ADC
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
3
2
VREF ERROR (mV)
1
0
–1
Figure 42. Internal Reference Configuration
In either internal or external reference mode, the maximum
input range of the ADC can be varied by configuring SPI
Address 0x18 as shown in Table 11, resulting in a selectable
differential span from 1 V p-p to 2 V p-p.
If the internal reference of the AD9609 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
–2
–3
–4
–5
–6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 44. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 27). The internal buffer generates the posi-
tive and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage (V)
Fixed Internal Reference
AGND to 0.2
Fixed External Reference
AVDD
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
Resulting Differential Span (V p-p)
2.0
2.0
Table 11. Scaled Differential Span Summary
Selected Mode
Resulting VREF (V)
Fixed Internal or External Reference 1.0 (internal or external)
Fixed Internal or External Reference 1.0 (internal or external)
Fixed Internal or External Reference 1.0 (internal or external)
Fixed Internal or External Reference 1.0 (internal or external)
Fixed Internal or External Reference 1.0 (internal or external)
SPI Register 0x18 (Hex)
0xC0
0xC8
0xD0
0xD8
0xE0
Rev. 0 | Page 19 of 32
Resulting Differential Span (V p-p)
1.0
1.14
1.33
1.6
2.0
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