AD9520-4BCPZ-REEL7 View Datasheet(PDF) - Analog Devices

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AD9520-4BCPZ-REEL7

12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

Analog Devices 

AD9520-4

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 7

Clock Outputs ............................................................................... 7

Timing Characteristics ................................................................ 8

Timing Diagrams ..................................................................... 9

Clock Output Additive Phase Noise (Distribution Only; VCO

Divider Not Used) ...................................................................... 10

Clock Output Absolute Phase Noise (Internal VCO Used).. 11

Clock Output Absolute Time Jitter (Clock Generation Using

Internal VCO) ............................................................................. 11

Mode 1: Clock Distribution or External

VCO <1600 MHz ................................................................... 30

Mode 2: High Frequency Clock Distribution—CLK or

External VCO > 1600 MHz .................................................. 32

Phase-Locked Loop (PLL) .................................................... 34

Configuration of the PLL ...................................................... 34

Phase Frequency Detector (PFD) ........................................ 34

Charge Pump (CP)................................................................. 35

On-Chip VCO ........................................................................ 35

PLL External Loop Filter....................................................... 35

PLL Reference Inputs............................................................. 35

Reference Switchover............................................................. 36

Reference Divider R ............................................................... 36

VCXO/VCO Feedback Divider N: P, A, B, R ..................... 36

Digital Lock Detect (DLD) ................................................... 38

Analog Lock Detect (ALD)................................................... 38

Current Source Digital Lock Detect (CSDLD) .................. 38

Clock Output Absolute Time Jitter (Clock Cleanup Using

External VCXO/VCO Clock Input (CLK/CLK) ................ 39

Internal VCO) ............................................................................. 11

Holdover.................................................................................. 39

Clock Output Absolute Time Jitter (Clock Generation Using

External VCXO) ......................................................................... 12

Clock Output Additive Time Jitter (VCO Divider Not Used)

....................................................................................................... 12

Manual Holdover Mode ........................................................ 39

Automatic/Internal Holdover Mode.................................... 39

Frequency Status Monitors ................................................... 41

Clock Output Additive Time Jitter (VCO Divider Used) ..... 13

VCO Calibration .................................................................... 42

Serial Control Port—SPI Mode ................................................ 13

Zero Delay Operation................................................................ 43

Serial Control Port—I2C Mode ................................................ 14

Internal Zero Delay Mode..................................................... 43

PD, SYNC, and RESET Pins ..................................................... 15

External Zero Delay Mode.................................................... 43

Serial Port Setup Pins: SP1, SP0 ............................................... 15

Clock Distribution ..................................................................... 44

LD, STATUS, REFMON Pins.................................................... 15

Operation Modes ................................................................... 44

Power Dissipation....................................................................... 16

CLK or VCO Direct-to-LVPECL Outputs.......................... 44

Absolute Maximum Ratings.......................................................... 17

Clock Frequency Division..................................................... 45

Thermal Resistance .................................................................... 17

VCO Divider........................................................................... 45

ESD Caution................................................................................ 17

Channel Dividers ................................................................... 45

Pin Configuration and Function Descriptions........................... 18

Synchronizing the Outputs—SYNC Function ................... 47

Typical Performance Characteristics ........................................... 21

LVPECL Output Drivers ....................................................... 48

Terminology .................................................................................... 26

CMOS Output Drivers .......................................................... 49

Detailed Block Diagram ................................................................ 27

Reset Modes ................................................................................ 49

Theory of Operation ...................................................................... 28

Power-On Reset...................................................................... 49

Operational Configurations...................................................... 28

Hardware Reset via the RESET Pin ..................................... 49

Mode 0: Internal VCO and Clock Distribution ................. 28

Soft Reset via the Serial Port................................................. 49

Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via

the Serial Port ......................................................................... 49

Rev. 0 | Page 2 of 84

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