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AD9650BCPZRL7-65 View Datasheet(PDF) - Analog Devices

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AD9650BCPZRL7-65 Datasheet PDF : 44 Pages
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AD9650
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1
Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS
Enabled
Divide-by-1 Mode, DCS
Disabled
Divide-by-2 Mode
Through Divide-by-8
Mode
Aperture Delay (tA)
Aperture Uncertainty
(Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay
(tPD)
DCO Propagation Delay
(tDCO) 2
DCO to Data Skew (tSKEW)
LVDS Mode
Data Propagation Delay
(tPD)
DCO Propagation Delay
(tDCO)2
DCO to Data Skew (tSKEW)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/
Channel B
Wake-Up Time3
Out-of-Range Recovery
Time
AD9650BCPZ-25
AD9650BCPZ-65
AD9650BCPZ-80
AD9650BCPZ-105
Temp Min Typ
Max Min Typ
Max Min Typ
Max Min Typ
Max Unit
Full
200
520
640
640 MHz
Full 20
Full 10
Full 40
25 20
25 10
15.4
65 20
65 10
12.5
80 20
80 10
9.5
105 MSPS
105 MSPS
ns
Full 12 20
Full 19 20
Full 0.8
28 4.65 7.70
21 7.33 7.70
0.8
10.75 3.75 6.25
8.07 5.95 6.25
0.8
8.75 2.85 4.75
6.55 4.5 4.75
0.8
6.65 ns
5.0 ns
ns
Full
1.0
Full
0.100
1.0
0.090
1.0
0.080
1.0
0.075
ns
ps rms
Full 2.8 3.5
4.2 2.8 3.5
4.2 2.8 3.5
4.2 2.8 3.5
4.2 ns
Full
3.1
3.1
3.1
3.1
ns
Full −0.6 −0.4
0
−0.6 −0.4
0
−0.6 −0.4
0
−0.6 −0.4
0
ns
Full 2.9 3.7
4.5 2.9 3.7
4.5 2.9 3.7
4.5 2.9 3.7
4.5 ns
Full
3.9
3.9
3.9
3.9
ns
Full −0.1 +0.2
Full
12
+0.5 −0.1 +0.2
12
+0.5 −0.1 +0.2
12
+0.5 −0.1 +0.2
12
+0.5 ns
Cycles
Full
12/12.5
12/12.5
12/12.5
12/12.5
Cycles
Full
500
500
500
500
μs
Full
2
2
2
2
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. 0 | Page 7 of 44
 

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