AD9648BCPZRL7-105 View Datasheet(PDF) - Analog Devices
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Description
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AD9648BCPZRL7-105 Datasheet PDF : 44 Pages
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AD9648
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING
REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING
REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Description
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge
Limit
0.24
0.40
2
2
40
2
2
10
10
10
10
Unit
ns typ
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Timing Diagrams
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
N – 17
N – 16
N – 15
N – 14
tPD
Figure 2. CMOS Default Output Mode Data Output Timing
N – 13
N – 12
Rev. 0 | Page 9 of 44
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