AD9648BCPZ-105 View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD9648BCPZ-105 Datasheet PDF : 44 Pages
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AD9648
VIN
CLK+
CLK–
DCOA/DCOB
CH A DATA
CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
CH A CH B CH A CH B CH A CH B CH A CH B
N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9
tPD
CH B CH A CH B CH A CH B CH A CH B CH A
N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9
CH A
N–8
CH B
N–8
Figure 3. CMOS Interleaved Output Mode Data Output Timing
VIN
CLK+
CLK–
DCO+
DCO–
PARALLEL
INTERLEAVED
MODE
D0+ (LSB)
D0– (LSB)
D13+ (MSB)
D13– (MSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL A
D1+/0+ (LSB)
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL B
D1+/D0+ (LSB)
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tPD
tSKEW
CH A CH B CH A CH B CH A CH B CH A
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9
CH B
N–9
CH A
N–8
CH A CH B CH A CH B CH A CH B CH A
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9
CH B
N–9
CH A
N–8
CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0 CH A1 CH A0
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12 CH A13 CH A12
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0 CH B1 CH B0
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
CH B12 CH B13 CH B12 CH B13 CH B12 CH B13 CH A12 CH A13 CH A12
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
Figure 4. LVDS Modes for Data Output Timing
Rev. 0 | Page 10 of 44
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