AD9642-210EBZ View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9642-210EBZ

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)

Analog Devices 

AD9642

Data Sheet

SWITCHING SPECIFICATIONS

Table 4.

Parameter

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate1

CLK Period—Divide-by-1 Mode (tCLK)

CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-2 Mode Through

Divide-by-8 Mode

Aperture Delay (tA)

Aperture Uncertainty (Jitter, tJ)

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

DCO Propagation Delay (tDCO)

DCO-to-Data Skew (tSKEW)

Pipeline Delay (Latency)

Wake-Up Time (from Standby)

Wake-Up Time (from Power-Down)

Out-of-Range Recovery Time

Temp

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

Full

1 Conversion rate is the clock rate after the divider.

AD9642-170

Min Typ Max

AD9642-210

Min Typ Max

625

625

40

170 40

210

5.8

4.8

2.61 2.9 3.19 2.16 2.4 2.64

2.76 2.9 3.05 2.28 2.4 2.52

0.8

0.8

1.0

1.0

0.1

0.1

4.1

4.7

5.2

4.1

4.7

5.2

4.7

5.3

5.8

4.7

5.3

5.8

0.3 0.5 0.7 0.3 0.5 0.7

10

10

10

10

100

100

3

3

AD9642-250

Min Typ Max Unit

625 MHz

40

250 MSPS

4

ns

1.8 2.0 2.2 ns

1.9 2.0 2.1 ns

0.8

ns

1.0

ns

0.1

ps rms

4.1

4.7

5.2 ns

4.7

5.3

5.8 ns

0.3 0.5 0.7 ns

10

Cycles

10

μs

100

μs

3

Cycles

Timing Diagram

VIN

CLK+

CLK–

DCO–

DCO+

D0±/D1±

EVEN/ODD (LSB)

D12±/D13±

(MSB)

N–1

tCH

tA

N

N+1

tCLK

N+2

N+3

N+4

N+5

tDCO

tSKEW

tPD

D0

D1

N – 10 N – 10

D0

N–9

D1

N–9

D0

N–8

D1

N–8

D0

N–7

D1

N–7

D0

N–6

D12

D13

N – 10 N – 10

D12

N–9

D13

N–9

Figure 2. LVDS Data Output Timing

D12

N–8

D13

N–8

D12

N–7

D12

N–7

D12

N–6

Rev. B | Page 6 of 28

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