AD9558BCPZ View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD9558BCPZ Datasheet PDF : 104 Pages
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Data Sheet
AD9558
REFERENCE INPUTS
Table 7.
Parameter
DIFFERENTIAL OPERATION
Frequency Range
Sinusoidal Input
LVPECL Input
Min
Typ
10
0.002
LVDS Input
0.002
Minimum Input Slew Rate
40
Common-Mode Input Voltage
AC-Coupled
1.9
2
DC-Coupled
1.0
Differential Input Voltage Sensitivity
fIN < 800 MHz
240
fIN = 800 to 1050 MHz
320
fIN = 1050 to 1250 MHz
400
Differential Input Voltage Hysteresis
58
Input Resistance
21
Input Capacitance
3
Minimum Pulse Width High
LVPECL
LVDS
Minimum Pulse Width Low
LVPECL
LVDS
SINGLE-ENDED OPERATION
Frequency Range (CMOS)
Minimum Input Slew Rate
Input Voltage High (VIH)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Voltage Low (VIL)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
390
640
390
640
0.002
40
1.0
1.4
2.0
47
3
1.5
1.5
Max Unit Test Conditions/Comments
750 MHz
1250 MHz The reference input divide-by-2 block must be
engaged for fIN > 705 MHz
750 MHz The reference input divide-by-2 block must be
engaged for fIN > 705 MHz
V/μs Minimum limit imposed for jitter performance
2.2
V
Internally generated
2.4
V
mV Minimum differential voltage across pins is required to
ensure switching between logic levels; instantaneous
voltage on either pin must not exceed the supply rails
mV
mV
mV
100 mV
kΩ
pF
ps
ps
ps
ps
300 MHz
V/μs Minimum limit imposed for jitter performance
V
V
V
0.35 V
0.5
V
1.0
V
kΩ
pF
ns
ns
Rev. A | Page 7 of 104
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