AD9558 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9558

Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync

Analog Devices 

Data Sheet

AD9558

POWER DISSIPATION

Table 3.

Parameter

POWER DISSIPATION

Typical Configuration

Min Typ Max Unit

0.47 0.74 1.02 W

All Blocks Running

0.6 1.0 1.32 W

Full Power-Down

44

125 mW

Incremental Power Dissipation

Input Reference On/Off

Differential Without Divide-by-2 20

25

32

mW

Differential With Divide-by-2

26

32

40

mW

Single-Ended (Without Divide-by-2) 5

7

9

mW

Output Distribution Driver On/Off

LVDS (at 750 MHz)

12

17

22

mW

HSTL (at 750 MHz)

14

21

28

mW

1.8 V CMOS (at 250 MHz)

14

21

28

mW

3.3 V CMOS (at 250 MHz)

18

27

36

mW

Other Blocks On/Off

Second RF Divider

36

51

64

mW

Channel Divider Bypassed

10

17

23

mW

LOGIC INPUTS (SYNC, RESET, PINCONTROL, M7 TO M0)

Table 4.

Parameter

Min Typ

LOGIC INPUTS (SYNC, RESET, PINCONTROL)

Input High Voltage (VIH)

2.1

Input Low Voltage (VIL)

Input Current (IINH, IINL)

±50

Input Capacitance (CIN)

3

LOGIC INPUTS (M7 to M0)

Input High Voltage (VIH)

2.5

Input ½ Level Voltage (VIM)

1.0

Input Low Voltage (VIL)

Input Current (IINH, IINL)

±60

Input Capacitance (CIN)

3

Max Unit

V

0.8

V

±100 μA

pF

V

2.2

V

0.6

V

±100 μA

pF

Test Conditions/Comments

System clock: 49.152 MHz crystal; DPLL active;

both 19.44 MHz input references in differential mode;

one HSTL driver at 644.53125 MHz;

one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF

capacitive load on CMOS output

System clock: 49.152 MHz crystal; DPLL active;

both input references in differential mode;

four HSTL drivers at 750 MHz;

four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive

load on CMOS outputs

Typical configuration with no external pull-up or pull-

down resistors; about 2/3 of this power is on AVDD3

Conditions = typical configuration; table values show the

change in power due to the indicated operation

Additional current draw is in the DVDD3 domain only

Additional current draw is in the DVDD3 domain only

Additional current draw is in the DVDD3 domain only

Additional current draw is in the AVDD domain only

Additional current draw is in the AVDD domain only

A single 1.8 V CMOS output with an 80 pF load

A single 3.3 V CMOS output with an 80 pF load

Additional current draw is in the AVDD domain only

Additional current draw is in the AVDD domain only

Test Conditions/Comments

Rev. A | Page 5 of 104

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