AD9252 View Datasheet(PDF) - Analog Devices
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AD9252 Datasheet PDF : 52 Pages
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AD9252
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
An 8-, 10-, and 12-bit serial stream can also be initiated from
the SPI. This allows the user to implement different serial stream
to test the device’s compatibility with lower and higher resolution
systems. When changing the resolution to an 8-, 10-, or 12-bit
serial stream, the data stream is shortened. See Figure 3 for a
12-bit example.
When the SPI is used, the data outputs can be inverted from
their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as
shown in Figure 2, the MSB is first in the data output serial
stream. However, this can be inverted so that the LSB is first in
the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, customer user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options except PN sequence short and PN sequence long can
support 8- to 14-bit word lengths in order to verify data capture
to the receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A description
of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9252 inverts the bit stream with relation to the ITU standard.
Table 10. PN Sequence
Sequence
Initial
Value
PN Sequence Short 0x0df
PN Sequence Long
0x26e028
First Three Output Samples
(MSB First)
0x37e4, 0x3533, 0x0063
0x191f, 0x35c2, 0x2359
Data Sheet
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 kΩ internal
pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
If applications require this pin to be driven from a 3.3 V logic level,
insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Resulting
Selected ODM ODM Voltage Output Standard
Normal
Operation
AGND
(10 kΩ pull-
down resistor)
ANSI-644
(default)
ODM
AVDD
Low power,
reduced signal
option
Resulting
FCO and DCO
ANSI-644
(default)
Low power,
reduced signal
option
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test pattern
if it and the CSB pin are held high during device power-up. When
the SCLK/DTP is tied to AVDD, the ADC channel outputs shift
out the following pattern: 10 0000 0000 0000. The FCO and DCO
function normally while all channels shift out the repeatable test
pattern. This pattern allows the user to perform timing alignment
adjustments among the FCO, DCO, and output data. For normal
operation, this pin should be tied to AGND through a 10 kΩ
resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage
Resulting
D + x and D − x
Normal
Operation
AGND
(10 kΩ pull-
down resistor)
Normal
operation
DTP
AVDD
10 0000 0000
0000
Resulting
FCO and DCO
Normal operation
Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options available.
Rev. E | Page 24 of 52
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