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AD9252 View Datasheet(PDF) - Analog Devices

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AD9252 Datasheet PDF : 52 Pages
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AD9252
Data Sheet
500
400
300
200
100
0
–100
–200
–300
–400
–500
EYE: ALL BITS
–1.5ns –1.0ns –0.5ns 0ns
ULS: 12071/12071
0.5ns 1.0ns 1.5ns
400
300
200
100
0
–100
–200
–300
–400
EYE: ALL BITS
–1.5ns –1.0ns –0.5ns
0ns
ULS: 12072/12072
0.5ns 1.0ns 1.5ns
90
80
70
60
50
40
30
20
10
0
–150ps –100ps –50ps
0ps
50ps 100ps 150ps
Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less Than 24 Inches on Standard FR-4
500
EYE: ALL BITS
400
300
200
100
0
–100
–200
–300
–400
–500
–1.5ns –1.0ns –0.5ns 0ns
ULS: 12067/12067
0.5ns 1.0ns 1.5ns
100
90
80
70
60
50
40
30
20
10
0
–200ps
–100ps
0ps
100ps
200ps
Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4
80
70
60
50
40
30
20
10
0
–150ps –100ps –50ps
0ps
50ps 100ps 150ps
Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
(VIN + x) − (VIN − x),
Code Input Span = 2 V p-p (V)
16383 +1.00
8192 0.00
8191 −0.000122
0
−1.00
Digital Output Offset Binary
(D13 ... D0)
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 14 bits
times the sample clock rate, with a maximum of 700 Mbps
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
information about enabling this feature.
Rev. E | Page 22 of 52
 

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