AD9252 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9252

Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC

Analog Devices 

AD9252

Data Sheet

For best dynamic performance, the source impedances driving

VIN + x and VIN − x should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference buffer

creates the positive and negative reference voltages, REFT and

REFB, respectively, that define the span of the ADC core. The

output common mode of the reference buffer is set to midsupply,

and the REFT and REFB voltages and span are defined as

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

It can be seen from these equations that the REFT and REFB

voltages are symmetrical about the midsupply voltage and, by

definition, the input span is twice the value of the VREF voltage.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9252, the largest input span available is 2 V p-p.

Differential Input Configurations

There are several ways to drive the AD9252 either actively or

passively; however, optimum performance is achieved by driving

the analog input differentially. For example, using the AD8334

differential driver to drive the AD9252 provides excellent perfor-

mance and a flexible interface to the ADC (see Figure 39) for

baseband applications. This configuration is commonly used

for medical ultrasound systems.

For applications where SNR is a key parameter, differential

transformer coupling is the recommended input configuration

(see Figure 36 and Figure 37), because the noise performance of

most amplifiers is not adequate to achieve the true performance

of the AD9252.

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

0.1μF

ADT1-1WT

1:1 Z RATIO

RC

2V p-p

49.9Ω

AVDD

1kΩ

CDIFF1

R

C

VIN + x

ADC

AD9252

VIN – x

AGND

1kΩ

0.1μF

1CDIFF IS OPTIONAL.

Figure 36. Differential Transformer-Coupled Configuration

for Baseband Applications

2V p-p

16nH

0.1μF

ADT1-1WT

1:1 Z RATIO

16nH

33Ω

65Ω

499Ω 2.2pF

1kΩ

16nH 33Ω

AVDD

1kΩ

VIN+ x

ADC

AD9252

VIN– x

1kΩ

0.1μF

Figure 37. Differential Transformer-Coupled Configuration for IF Applications

Single-Ended Input Configuration

A single-ended input may provide adequate performance in cost-

sensitive applications. In this configuration, SFDR and distortion

performance degrade due to the large input common-mode swing.

If the application requires a single-ended input configuration,

ensure that the source impedances on each input are well matched

in order to achieve the best possible performance. A full-scale input

of 2 V p-p can still be applied to the ADC’s VIN + x pin while the

VIN − x pin is terminated. Figure 38 details a typical single-

ended input configuration.

AVDD

2V p-p

C

1kΩ

R

49.9Ω

0.1µF 1kΩ

AVDD

CDIFF1

1kΩ 25Ω

R

0.1µF 1kΩ

C

VIN + x

ADC

AD9252

VIN – x

1CDIFF IS OPTIONAL.

Figure 38. Single-Ended Input Configuration

1V p-p

LOP

VIP

0.1μF 120nH

INH

AD8334

22pF

LNA

VOH

VGA

0.1μF

LMD

LON

VOL

VIN

18nF 274Ω

0.1μF

187Ω 0.1μF

374Ω

1.0kΩ

1.0kΩ

187Ω

0.1μF

0.1μF

R

VIN + x

C

ADC

AD9252

R

VIN – x

AVDD

10μF

1kΩ

1kΩ

Figure 39. Differential Input Configuration Using the AD8334

Rev. E | Page 18 of 52

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