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AD9237 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD9237 Datasheet PDF : 28 Pages
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Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 34.2 MHz
fINPUT = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 34.2 MHz
fINPUT = 70 MHz
WORST OTHER SPUR
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 34.2 MHz
fINPUT = 70 MHz
AD9237
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Min Typ Max Min Typ Max Min Typ Max Unit
88.0
83.5
85.5
dBc
72.4 87.5
dBc
72.2 82.4
dBc
69.4 80.1
dBc
80.5
77.9
74.9
dBc
−88.0
−83.5
−85.5
dBc
−72.4 −87.5
dBc
−72.2 −82.4
dBc
−69.4 −80.1
dBc
−80.5
−77.9
−74.9
dBc
−90
−90
−90
dBc
−73.4 −90
dBc
−73.1 −90
dBc
−72.0 −90
dBc
−90
−90
−90
dBc
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1
CLK Pulse Width Low1
DATA OUTPUT PARAMETERS
Output Delay (tPD)2
Pipeline Delay (Latency)
Output Enable Time
Output Disable Time
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time (Sleep Mode)3
Wake-Up Time (Standby Mode)3
OUT-OF-RANGE RECOVERY TIME
AD9237BCP-20
Min Typ Max
AD9237BCP-40
Min Typ Max
AD9237BCP-65
Min Typ Max
20
40
65
1
1
1
50.0
25.0
15.4
15.0
8.8
6.2
15.0
8.8
6.2
3.5
3.5
3.5
8
8
8
6
6
6
3
3
3
1.0
1.0
1.0
0.5
0.5
0.5
3.0
3.0
3.0
3.0
3.0
3.0
1
1
2
1 With duty cycle stabilizer enabled.
2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ns
ns
ps rms
ms
μs
Cycles
Rev. 0 | Page 5 of 28
 

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