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AD9148BBCZRL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9148BBCZRL Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter ADI
Analog Devices ADI
AD9148BBCZRL Datasheet PDF : 72 Pages
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Data Sheet
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation (with or Without Coarse Modulation)
2× Interpolation (with or Without Coarse Modulation)
4× Interpolation (with or Without Coarse Modulation)
8× Interpolation (with or Without Coarse Modulation)
Inverse Sinc (1× Interpolation)
Inverse Sinc (2× Interpolation)
Inverse Sinc (4× Interpolation)
Inverse Sinc (8× Interpolation)
Fine Modulation
Power–Up Time
Table 4. Maximum Rate
Interface Mode
Dual Port Mode
Single Port Mode or Byte Mode
fINTERFACE
620
1200
AD9148
Min
Typ
Max
Unit
64
Cycles
125
Cycles
254
Cycles
508
Cycles
10
Cycles
20
Cycles
40
Cycles
80
Cycles
12
Cycles
100
ms
Maximum Rate (MSPS)
fDATA
fHB1
fHB2
310
620
1000
300
600
1000
fHB3
1000
1000
fDAC
1000
1000
32
DATA
PORT A
INPUT
LATCH
DATA
ASSEMBLER
32
FIFO A
DATAPATH
32 DAC1
AND
DAC2
DCIA
WRITE PTR A
CLK GENERATOR
AND DISTRIBUTOR
DATAPATH
DACCLK
DCIB
ONE DCI
WRITE PTR B
DATA
PORT B
INPUT
LATCH
DATA
ASSEMBLER
32
32
32
DAC3
AND
FIFO B
DAC4
fINTERFACE
INTERFACE
MODE
fDATA
fHB1
fHB2
fHB3
fDAC
Figure 3. Defining Maximum Rates
Rev. B | Page 7 of 72
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