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AD9148BBCZ View Datasheet(PDF) - Analog Devices

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AD9148BBCZ Datasheet PDF : 72 Pages
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AD9148
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
DCIA_P/
DCIA_N
FRAMEA_P/
FRAMEA_N
1.2GHz
A[15:0]_P/ 16
A[15:0]_N
310MHz
fS/2
MOD
fS/2
MOD
B[15:0]_P/ 16
B[15:0]_N
FRAMEB_P/
FRAMEB_N
DCIB_P/
DCIB_N
fS/2
MOD
fS/2
MOD
PROGRAMMING
REGISTERS
310MHz
SINC–1
310MHz/620MHz
500MHz/1GHz
500MHz/1GHz
SINC–1
SINC–1
COS
32-BIT
NCO SIN
SINC–1
INTERNAL CLOCK TIMING AND CONTROL LOGIC
SERIAL
IN/OUT PORT
POWER-ON
RESET
MULTI-CHIP
SYNC
SYNC
1GHz
16-BIT
DAC1
I OFFSET I GAIN
Q OFFSET Q GAIN
GAIN
AUX1
16-BIT
DAC2
GAIN
AUX2
16-BIT
DAC3
I OFFSET I GAIN
Q OFFSET Q GAIN
GAIN
AUX3
16-BIT
DAC4
GAIN
AUX4
GAIN/
OFFSET_CTR L
PLL_CTR L
REFERENCE
BIAS
DAC_CLK
CLOCK
MULTIPLIER
(2× – 16×)
IOUT1_P
IOUT1_N
AUX1_P
AUX1_N
IOUT2_P
IOUT2_N
AUX2_P
AUX2_N
IOUT3_P
IOUT3_N
AUX3_P
AUX3_N
IOUT4_P
IOUT4_N
AUX4_P
AUX4_N
VREF
I120
CLK_P
CLK_N
REFCLK_P/
SYNC_ P
REFCLK_N/
SYNC_N
Figure 2.
Rev. B | Page 4 of 72
 

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