AD9148-EBZ View Datasheet(PDF) - Analog Devices
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AD9148-EBZ Datasheet PDF : 72 Pages
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Data Sheet
Quad 16-Bit,1 GSPS,
TxDAC+ Digital-to-Analog Converter
AD9148
FEATURES
Single-carrier W-CDMA ACLR = 80 dBc at 150 MHz IF
Channel-to-channel isolation > 90 dB
Analog output
Adjustable 8.7 mA to 31.7 mA
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator eases data interface
On-chip fine complex NCO allows carrier placement
anywhere in DAC bandwidth
High performance, low noise PLL clock multiplier
Multiple chip synchronization interface
Programmable digital inverse sinc filter
Auxiliary DACs allow for offset control
Gain DACs allow for I and Q gain matching
Programmable I and Q phase compensation
Digital gain control
Flexible LVDS digital I/F supports 32- or 16-bit bus width
196-ball CSP_BGA, 12 mm × 12 mm
APPLICATIONS
Wireless infrastructure
LTE, TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM
MIMO/transmit diversity
Digital high or low IF synthesis
GENERAL DESCRIPTION
The AD9148 is a quad, 16-bit, high dynamic range, digital-to-
analog converter (DAC) that provides a sample rate of 1000 MSPS.
This device includes features optimized for direct conversion
transmit applications, including gain, phase, and offset compen-
sation. The DAC outputs are optimized to interface seamlessly with
analog quadrature modulators such as the ADL5371/ADL5372/
ADL5373/ADL5374/ADL5375. A serial peripheral interface (SPI)
is provided for programming of the internal device parameters.
Full-scale output current can be programmed over a range of 8.7 mA
to 31.7 mA. The device operates from 1.8 V and 3.3 V supplies
for a total power consumption of 3 W at the maximum sample
rate. The AD9148 is enclosed in a 196-ball chip scale package ball
grid array with the option of an attached heat spreader.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. The LVDS data input interface includes FIFO to ease input
timing.
TYPICAL SIGNAL CHAIN
COMPLEX BASEBAND
COMPLEX IF
RF
DC
FPGA/ASIC/DSP
fIF
DIGITAL INTERPOLATION FILTERS
↑2
↑2
↑2
DAC1
↑2
↑2
↑2
DAC2
LO ± fIF
POST DAC
ANALOG FILTER
AQM PA
LO
↑2
↑2
↑2
DAC3
↑2
↑2
↑2
DAC4
POST DAC
LO
AQM PA
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
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