AD9125BCPZRL View Datasheet(PDF) - Analog Devices
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AD9125BCPZRL Datasheet PDF : 56 Pages
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AD9125
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
CMOS DATA INPUTS
Input VIN Logic High
Input VIN Logic Low
Maximum Bus Speed
SERIAL PORT OUTPUT LOGIC LEVELS
Output VOUT Logic High
Output VOUT Logic Low
SERIAL PORT INPUT LOGIC LEVELS
Input VIN Logic High
Input VIN Logic Low
DACCLK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK INPUT (REFCLKP, REFCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLKx Frequency, PLL Mode
REFCLKx Frequency, SYNC Mode
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High (tPWH)
Minimum Pulse Width Low (tPWOL)
Setup Time, SDI to SCLK (tDS)
Hold Time, SDI to SCLK (tDH)
Data Valid, SDO to SCLK (tDV)
Setup Time, CS to SCLK (tDCS)
Conditions
Min Typ Max Unit
1.2
V
0.6 V
250
MHz
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
1.4
V
1.8
V
2.0
V
0.4
0.4 V
0.4 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3 V
IOVDD = 1.8 V
IOVDD = 2.5 V
IOVDD = 3.3V
1.2
V
1.6
V
2.4
V
0.6 V
0.8 V
0.8 V
Self biased input, ac couple
100
1000
500 2000 mV
1.25
V
MHz
100
500 2000 mV
1.25
V
1 GHz ≤ fVCO ≤ 2.1 GHz
15.625
600 MHz
See the Multichip Synchronization section for conditions 0
600 MHz
40
MHz
12.5 ns
12.5 ns
1.9
ns
0.2
ns
2.3
ns
1.4
ns
LATENCY AND POWER-UP TIMING SPECIFICATIONS
Table 3.
Parameter
LATENCY (DACCLK Cycles)
1× Interpolation (with or Without Modulation)
2× Interpolation (with or Without Modulation)
4× Interpolation (with or Without Modulation)
8× Interpolation (with or Without Modulation)
Inverse Sinc
Fine Modulation
Power-Up Time
Rev. 0 | Page 5 of 56
Min
Typ
Max
64
135
292
608
20
8
260
Unit
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
ms
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