AD9125
SERIAL PORT OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB-first), the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from the high address to the low address. In
MSB-first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communi-
cation cycle.
When LSB_FIRST = 1 (LSB-first), the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations
if the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x7F for
multibyte I/O operations if the LSB-first mode is active.
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6N D5N
D30 D20 D10 D00
D7 D6N D5N
D30 D20 D10 D00
Figure 38. Serial Register Interface Timing, MSB First
CS
SCLK
SDIO
SDO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
D00 D10 D20
D4N D5N D6N D7N
Figure 39. Serial Register Interface Timing, LSB First
tDS
tSCLK
CS
tPWH
tPWL
SCLK
SDIO
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 40. Timing Diagram for Serial Port Register Write (tDS to tDCS)
CS
SCLK
SDIO,
SDO
tDV
DATA BIT n
DATA BIT n – 1
Figure 41. Timing Diagram for Serial Port Register Read
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