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AD9129 View Datasheet(PDF) - Analog Devices

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AD9129 Datasheet PDF : 68 Pages
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AD9119/AD9129
CLOCK INPUT
The AD9119/AD9129 contain a low jitter, differential clock
receiver that is capable of interfacing directly to a differential
or single-ended clock source. Because the input is self-biased to
a nominal midsupply voltage of 1.25 V with a nominal impedance
of 10 kΩ//2 pF, it is recommended that the clock source be
ac-coupled to the DACCLK_x input pins with an external
differential load of 100 Ω. When the nominal differential input
span is 1 V p-p, the clock receiver can operate with a span that
ranges from 250 mV p-p to 2.0 V p-p.
DACCLK_P
DACCLK_N
5kΩ
5kΩ
1.25V
DUTY CYCLE
RESTORER
25µA
50k
TO DAC
AND DLL
Figure 147. Clock Input
The quality of the clock source, as well as its interface to the
AD9119/AD9129 clock input, directly impacts ac performance.
Select the phase noise and spur characteristics of the clock source
to meet the target application requirements. Phase noise and
spurs at a given frequency offset on the clock source are directly
translated to the output signal. It can be shown that the phase noise
characteristics of a reconstructed output sine wave are related to
the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock
path contribution is negligible. (The wideband noise is not
dominated by the thermal and quantization noise of the DAC.)
Figure 148 shows a clock source based on the ADF4350 low phase
noise/jitter PLL. The ADF4350 can provide output frequencies
from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. Its
squared-up output level can be varied from −4 dBm to +5 dBm,
allowing further optimization of the clock drive level.
Data Sheet
A clock control register exists at Address 0x30. This register can
be used to enable automatic duty cycle correction (Bit 1), enable
zero-crossing control (Bit 6), and set the zero-crossing point
(Bits[5:2]). Recommended settings for this register are listed in
the recommended start-up sequence section (see the Start-Up
Sequence section).
PLL
The DACCLK_x input goes to a high frequency PLL to ensure
robust locking of the DAC sample clock to the input clock. The
PLL is enabled by default such that the PLL locks upon power-up.
The PLL (or DAC clock retimer) control registers are located at
Register 0x33 and Register 0x34. Register 0x33 enables the user
to set the phase detector phase offset level (Bits[7:4]), clear the PLL
lost lock status bit (Bit 3), choose the PLL divider for optimum per-
formance (Bit 2), and choose the phase detector mode (Bits[1:0]).
These settings are determined during product characterization
and are given in the recommended start-up sequence (see the
Start-Up Sequence section). It is not normally necessary to change
these values, nor is the product characterization data valid on
any settings other than the recommended ones. Register 0x34 is
used to reset the PLL, should that become necessary.
At DACCLK = 2.8 GSPS, the lock time is about 10 µs. In most
situations, no action is required with the PLL. If the DACCLK
is changed and, especially, if it is changed multiple times, as in
a frequency hopping application, a phase slip or glitch may be
caused by the change in frequency, and it may become necessary
to reset the PLL. This can be checked by reading the PLL retimer
lost lock bit (Register 0x35, Bit 6). If that is the case, toggle the
PLL reset bit by programming Register 0x34, Bit 3, high and then
low. In addition, clear the PLL retimer lost lock bit by writing 0b
to Register 0x35, Bit 6. PLL lock can be verified by reading the
PLL lock bit at Register 0x35, Bit 7. It is possible to use the IRQ
registers to set an interrupt for these events. See the Interrupt
Requests section for more details.
ADF4350
fREF
PLL VCO
DIV-BY-2N
N=0–4
AD9129
2.4nF
2.4nF
100
DACCLK_P
DACCLK_N
0.8GHz TO 2.8GHz
1V p-p
Figure 148. Possible Signal Chain for DACCLK_x Input
Rev. 0 | Page 50 of 68
 

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