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AD9129BBCRL View Datasheet(PDF) - Analog Devices

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AD9129BBCRL Datasheet PDF : 68 Pages
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Data Sheet
ANALOG INTERFACE CONSIDERATIONS
ANALOG MODES OF OPERATION
The AD9119/AD9129 use the quad-switch architecture shown in
Figure 143. Only one pair of switches is enabled during a half-clock
cycle, thus requiring each pair to be clocked on alternative clock
edges. A key benefit of the quad-switch architecture is that it masks
the code-dependent glitches that occur in the conventional two-
switch DAC architecture.
DACCLK_x
CLK
VG1
IOUTP
IOUTN
VG2
LATCHES VG3
VG1
Px_D[13:0]x
VG4
VG2 VG3
VG4
VSSA
Figure 143. Quad-Switch Architecture
In two-switch architecture, when a switch transition occurs and
D1 and D2 are in different states, a glitch occurs. But, if D1 and
D2 happen to be at the same state, the switch transitions, and no
glitches occur. This code-dependent glitching causes an increased
amount of distortion in the DAC. In quad-switch architecture
(no matter what the codes are), there are always two switches
that are transitioning at each half-clock cycle, thus eliminating
the code-dependent glitches but, in the process, creating a constant
glitch at 2 × DACCLK. For this reason, a significant clock spur
at 2 × fDACCLK is evident in the DAC output spectrum.
INPUT
DATA
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
DACCLK_x
TWO-SWITCH
DAC OUTPUT
D1 D2 D3 D4 D5
t
D6 D7 D8 D9 D10
FOUR-SWITCH
DAC OUTPUT
D6 D7 D8 D9 D10 t
(NORMAL MODE) D1 D2 D3 D4 D5
Figure 144. Two-Switch and Quad-Switch DAC Waveforms
As a consequence of the quad-switch architecture enabling
updates on each half-clock cycle, it is possible to operate that
DAC core at 2× the DACCLK rate if new data samples are latched
into the DAC core on both the rising and falling edge of the
DACCLK. This notion serves as the basis when operating the
AD9119/AD9129 in either Mix-Mode or with the 2× interpo-
lation filter enabled. In each case, the DAC core is presented
with new data samples on each clock edge, albeit in Mix-Mode;
the falling edge sample is simply the complement of the rising
edge sample value.
AD9119/AD9129
When Mix-Mode is used, the output is effectively chopped at
the DAC sample rate. This has the effect of reducing the power
of the fundamental signal while increasing the power of the
images centered around the DAC sample rate, thus improving
the dynamic range of these images.
INPUT
DATA
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
DACCLK_x
FOUR-SWITCH
DAC OUTPUT
(fS MIX-MODE)
D3
D2
D4
D1
D5
–D8
–D7
–D6
–D9
–D10
t
–D1
–D5 D6
D10
–D2
–D4
D7
D9
–D3
D8
Figure 145. Mix-Mode Waveform
This ability to change modes provides the user the flexibility to
place a carrier anywhere in the first three Nyquist zones, depending
on the operating mode selected. Switching between baseband
and Mix-Mode reshapes the sinc roll-off inherent at the DAC
output. In baseband mode, the sinc null appears at fDACCLK
because the same sample latched on the rising clock edge is also
latched again on the falling clock edge, thus resulting in the
same ubiquitous sinc response of a traditional DAC. In Mix-
Mode, the complement sample of the rising edge is latched on
the falling edge, therefore pushing the sinc null to 2 × fDACCLK.
Figure 146 shows the ideal frequency response of both modes
with the sinc roll-off included.
FIRST
NYQUIST ZONE
SECOND
NYQUIST ZONE
THIRD
NYQUIST ZONE
0
MIX-MODE
–5
–10
–15
BASEBAND
MODE
–20
–25
–30
–35
0
0.25
0.50
0.75
1.00
1.25
1.50
NORMALIZED FREQUENCY RELATIVE TO fDACCLK (Hz)
Figure 146. Sinc Roll-Off for Baseband Mode and Mix-Mode Operation
The quad-switch can be configured via SPI (Register 0x19, Bit 0)
to operate in either baseband mode (0b) or Mix-Mode (1b).
Rev. 0 | Page 49 of 68
 

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