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AD9129-MIX-EBZ View Datasheet(PDF) - Analog Devices

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AD9129-MIX-EBZ Datasheet PDF : 68 Pages
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AD9119/AD9129
INTERFACE TIMING VALIDATION
The AD9119/AD9129 provide on-chip sample error detection
(SED) circuitry that simplifies verification of the input data
interface. The SED compares the input data samples captured
at the digital input pins with a set of comparison values. The
comparison values are loaded into registers through the SPI port.
Differences between the captured values and the comparison
values are detected and stored.
SAMPLE ERROR DETECTION (SED) OPERATION
The SED circuitry operates on a data set made up of eight
11-bit/14-bit input words, denoted as R0L, R1L, R0H, R1H,
F0L, F1L, F0H, and F1H. These represent the rising edge and
falling edge data of Data Port 0 and Data Port 1. (The AD9119/
AD9129 use both edges of the DCI clock to sample data on each
input port.) To properly align the input samples, the rising edge
data-words of the data ports (that is, RxL and RxH) are indicated
by asserting the FRAME signal for a minimum of two complete
input samples.
Figure 142 shows the input timing of the interface in word mode.
The FRAME signal can be issued once at the start of the data
transmission, or it can be asserted repeatedly at intervals coinciding
with the RxL and RxH data-words.
DCI
FRAME
P0[7:0]
R0L
F0L
P0[13:8]
R0H
F0H
P1[7:0]
R1L
F1L
P1[13:8]
R1H
F1H
Figure 142. Timing Diagram of FRAME Signal Required to Align Input Data
for SED
The SED has three flag bits (Register 0x50, Bit 0, Bit 1, and Bit 2)
that indicate the results of the input sample comparisons. The
SED fail bit (Register 0x50, Bit 0) is set when an error is detected
and remains set until cleared. The SED also provides registers that
indicate which input data bits experienced errors (Register 0x51
through Register 0x58). These bits are latched and indicate the
accumulated errors detected until cleared. To clear the SED
registers, write 1b to Register 0x50, Bit 6.
The autosample error detection (AED) mode is an autoclear
mode that has the following two effects:
AED mode activates the AED fail bit and the AED pass bit
(Register 0x50, Bit 1 and Bit 2).
AED mode changes the behavior of Register 0x51 through
Register 0x58.
Data Sheet
The compare pass bit is set if the last comparison indicates that
the sample is error free. The compare fail bit is set if an error is
detected. The compare fail bit is automatically cleared by the
reception of eight consecutive error-free comparisons. When
autoclear mode is enabled, Register 0x51 through Register 0x58
accumulate errors as previously described but reset to all 0s after
eight consecutive error-free sample comparisons are made.
The sample error, compare pass, and compare fail flags can be
configured to trigger an IRQ when active, if desired. This is
accomplished by enabling the appropriate bits in the event flag
register (Register 0x06, Bit 4, Bit 5, and Bit 6).
SED EXAMPLE
Normal Operation
The following example illustrates the SED configuration for
continuously monitoring the input data and assertion of an IRQ
when a single error is detected.
1. Write to the following registers to load the comparison values:
a) Register 0x51: SED Patt/Err R0L, Bits[7:0].
b) Register 0x52: SED Patt/Err R0H, Bits[13:8].
c) Register 0x53: SED Patt/Err R1L, Bits[7:0].
d) Register 0x54: SED Patt/Err R1H, Bits[13:8].
e) Register 0x55: SED Patt/Err F0L, Bits[7:0].
f) Register 0x56: SED Patt/Err F0H, Bits[13:8].
g) Register 0x57: SED Patt/Err F1L, Bits[7:0].
h) Register 0x58: SED Patt/Err F1H, Bits[13:8].
i) Comparison values can be chosen arbitrarily;
however, choosing values that require frequent
bit toggling provides the most robust test.
2. Enable the SED error detect flag to assert the IRQ pin.
a) Register 0x04: set to 0x10.
3. Begin transmitting the input data pattern.
4. Write three times to Register 0x50 to enable the SED.
a) Register 0x50: set to 0x80.
b) Register 0x50: set to 0xC0.
c) Register 0x50: set to 0x80.
If IRQ is asserted, read Register 0x50 and Register 0x51 through
Register 0x58 to verify that a SED error is detected and determine
which input bits are in error. The bits in Register 0x51 through
Register 0x58 are latched. This means that the bits indicate any
errors that occur on those bits throughout the test and not just
the errors that caused the error detected flag to be set.
Rev. 0 | Page 48 of 68
 

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