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AD9129-MIX-EBZ View Datasheet(PDF) - Analog Devices

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AD9129-MIX-EBZ Datasheet PDF : 68 Pages
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AD9119/AD9129
THEORY OF OPERATION
The AD9119/AD9129 are 11-bit/14-bit DACs that are capable of
reconstructing signal bandwidths up to 1.4 GHz while operating
with an input data rate up to 2.8 GSPS. Figure 128 shows a top
level functional diagram of the AD9119/AD9129. A high perfor-
mance NMOS DAC delivers a signal dependent, differential
current to a balanced external load referenced a nominal 1.8 V
analog supply. The current source array of the DAC is referenced
to an external −1.5 V supply, and its full-scale current, IOUTFS,
can be adjusted over a 9.5 mA to 34.4 mA span.
RESET
IRQ
I250U VREF
SDIO
SDO
CS
SCLK
FRM_x
(FRAME/
PARITY)
P0_D[13:0]P,
P0_D[13:0]N
DCI_x
SPI
DLL
AD9129
1.2V
MIX-
NORMAL MODE
BASEBAND
MODE
Tx DAC
CORE
IOUTP
IOUTN
P1_D[13:0]P,
P1_D[13:0]N
PLL
DCO_x
CLOCK
DISTRIBUTION
DCR
DACCLK_x
Figure 128. Functional Block Diagram of the AD9119/AD9129
A low jitter differential clock receiver is used to square up the
signal appearing at the DACCLK_x input that sets the update
rate of the DAC. The differential clock receiver can accept
sinusoidal signals with negligible noise spectral density degra-
dation if the input signal level is maintained above 0 dBm.
A +1 dB degradation occurs at a −5 dBm input, and degradation
increases as the signal approaches −10 dBm and its associated
+2 dB additional degradation. A duty cycle restorer (DCR),
following the clock receiver, ensures near 50% duty-cycle to the
subsequent circuitry. The output of the DCR serves as the
master clock and is routed directly to the DAC, as well as to a
clock distribution block that generates all critical internal and
external clocks. The clock source quality, as defined by its phase
noise characteristics, jitter, and drive capability, is an important
consideration in maintaining optimum ac performance.
The AD9119/AD9129 supports a source synchronous, LVDS
double data-rate (DDR) data interface to the host processor.
Two 11-bit/14-bit LVDS data ports (P0_DxP, P0_DxN and
P1_DxP, P1_DxN) are used to sample de-interleaved data from
the host on the rising and falling edge of the host DCI clock.
Data Sheet
This effectively reduces the bus interface speed to ½ the data
rate (for example, fDATA/2) with the DCI clock operating at fDATA/4.
An optional parity bit can also be sent along with the data to
enhance the robustness of the interface. In this case, a counter
is available to count parity errors and generate an interrupt
request (IRQ) when a programmable threshold is exceeded.
The AD9119/AD9129 provide the host with a DCO clock that is
equal to the DCI clock frequency to establish synchronous opera-
tion. A delay locked loop (DLL) with programmable phase offset
is used to generate an internal sampling clock with optimum edge
placement for the input data latches of the LVDS DDR receivers.
When data is latched into the AD9119/AD9129, an eight-sample-
deep FIFO is used to hand off the data between the host and the
AD9119/AD9129 clock domains. The FIFO can be reset with an
external synchronization signal, fSYNC, to ensure consistent pipeline
latency. The pipeline delay, from a sample being latched into the
data port to when it appears at the DAC output, varies depending
on the chosen configuration (see the Pipeline Delay (Latency)
section).
The de-interleaved data is reassembled into its original data stream
after passing into the internal clock domain of the AD9119/
AD9129. Because the quad-switch architecture of the DAC
updates its output on both the rising and falling edge (for example,
dual edge clocking) of the DACCLK signal, the following two
additional modes of operation are available:
A 2× interpolation filter can be selected to increase the
effective DAC update rate (fDAC) to be 2× the input data
rate, hence simplifying the analog postfiltering require-
ments and reducing the effects of alias harmonics in the
desired baseband region.
A Mix-Mode option essentially generates the complement
sample on the falling edge such that the original Nyquist
spectrum is shifted to fDACCLK, with the sinc null of the DAC
falling at 2 × fDACCLK.
The digital handoff between the digital domain and mixed signal
domain of a high speed DAC is critical in preserving its output
dynamic range. A phase locked loop (PLL) with programmable
phase offset is used to optimize the timing handoff between these
two clock domains. State machines are used to initialize both the
DLL and the PLL during the initial boot sequence after receiving
a stable DACCLK signal. Following initialization of the two loops,
they maintain optimum timing alignment over temperature, time,
and power supply variation. The AD9119/AD9129 also provide
IRQ capability to monitor the DLL, the PLL, and other internal
circuitry.
Rev. 0 | Page 38 of 68
 

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