AD9114 View Datasheet(PDF) - Analog Devices
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AD9114 Datasheet PDF : 48 Pages
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AD9114/AD9115/AD9116/AD9117
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 90) can be used
in a differential version of the single-ended buffer shown in
Figure 89. The same R-C network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs.
The feedback resistors, RFB, determine the differential peak-
to-peak signal swing by the formula
VOUT = 2 × RFB × IFS
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,
VMAX
= VREF × ⎜⎜⎝⎛1 +
RFB
RB
⎟⎟⎠⎞
VMIN = VMAX − RFB × IFS
The common-mode voltage of the differential output is
determined by the formula
VCM = VMAX – RFB × IFS
CF
RB
RFB
AD9114/AD9115/
AD9116/AD9117
RS
IOUTP 28
REFIO 34
C
AVSS 25
IOUTN 29
RS
–
ADA4841-2
+
+
ADA4841-2
–
VOUT
CF
RB
RFB
Figure 90. Single-Supply Differential Buffer
AUXILIARY DACs
The DACs of the AD9114/AD9115/AD9116/AD9117 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2
equals 0.5 V and the following equation describes the no load
output voltage:
VOUT
= 0.5 V − ⎜⎜⎝⎛ I DAC
−
1.5
RS
⎟⎟⎠⎞16
kΩ
Figure 91 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN and IAUXEN
bits and gating to prohibit RS < 3.2 kΩ.
RNG0
RNG1
AUXDAC
[9:0]
AVDD
RNG: 00 = 125µA fS
01 = 62µA fS
10 = 31µA fS
11 = 16µA fS
OFS2
OFS1
OFS0
(OFS > 4 = 4)
4kΩ 8kΩ 16kΩ 16kΩ
REFIO
2
16kΩ
–
OP AMP
+
AUX
PIN
Figure 91. AUXDAC Simplified Circuit Diagram
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that IAUXDAC is full scale at 0x000 and zero
at 0x1FF, as shown in Figure 92.
3.0
OP AMP OUTPUT VOLTAGE vs.
2.8
CHANGES IN R_OFFSET AND IDAC
2.6
2.4
R_OFFSET = 3.3kΩ
2.2
R_OFFSET = 4kΩ
R_OFFSET = 5.3kΩ
2.0
R_OFFSET = 8kΩ
1.8
R_OFFSET = 16kΩ
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 10 20 30 40 50 60 70 80 90 100 110 120 130
IDAC (µA)
Figure 92. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load,
AUXDAC 0x1FF to 0x000
Rev. 0 | Page 44 of 48
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