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AD9115-EBZ View Datasheet(PDF) - Analog Devices

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AD9115-EBZ Datasheet PDF : 48 Pages
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AD9114/AD9115/AD9116/AD9117
USING THE INTERNAL TERMINATION RESISTORS
The AD9117/AD9116/AD9115/AD9114 have four 62.5 Ω
termination internal resistors (two for each DAC output).
To use these resistors to convert the DAC output current to a
voltage, connect each DAC output pin to the adjacent load pin.
For example, on the I DAC, IOUTP must be shorted to RLIP
and IOUTN must be shorted to RLIN. In addition, the CMLI
or CMLQ pin must be connected to ground directly or through
a resistor. If the output current is at the nominal 20 mA and the
CMLI or CMLQ pin is tied directly to ground, this produces a
dc common-mode bias voltage on the DAC output equal to 0.5 V.
If the DAC dc bias needs to be higher than 0.5 V, an external
resistor can be connected between the CMLI or CMLQ pin and
ground. This part also has an internal common-mode resistor
that can be enabled. This is explained in the Using the Internal
Common-Mode Resistor section.
CML
RCM
I DAC
OR
Q DAC
62.5
62.5
RLIN
IOUTN
IOUTP
RLIP
Figure 86. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode
resistor, which can be used to increase the dc bias of the
DAC outputs. By default, the common-mode resistor is not
connected. When enabled, it can be adjusted from ~60 Ω to
~260 Ω. Each main DAC has an independent adjustment using
the lower six bits in Register 0x05 (IRCML[5:0]) and Register
0x08 (QRCML[5:0]).
260
240
220
200
180
160
140
120
100
80
60
0
8
16
24
32
40
48
56
CODE
Figure 87. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages in
the parts allowing them to run at higher dc output bias voltages.
When running the bias voltage below 0.9 V and an AVDD of
3.3 V, the parts perform optimally when the CMLx pins are tied
to ground. When the dc bias increases above 0.9 V, set the CMLx
pins at 0.5 V for optimal performance. The maximum dc bias
on the DAC output should be kept at or below 1.2 V when the
supply is 3.3 V. When the supply is 1.8 V, keep the dc bias close
to 0 V and connect the CMLx pins directly to ground.
Rev. 0 | Page 42 of 48
 

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