AD9114 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9114

Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters

Analog Devices 

AD9114/AD9115/AD9116/AD9117

SPI REGISTER DESCRIPTIONS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted.

Table 14.

Register

SPI Control

Address Bit Name

0x00

6 LSBFIRST

5 RESET

Power Down 0x01

Data Control 0x02

4 LNGINS

7 LDOOFF

6 LDOSTAT

5 PWRDN

4 Q DACOFF

3 I DACOFF

2 QCLKOFF

1 ICLKOFF

0 EXTREF

7 TWOS

5 IFIRST

4 IRISING

3 SIMULBIT

2 DCI_EN

1 DCOSGL

0 DCODBL

I DAC Gain

IRSET

0x03

0x04

5:0 I DACGAIN[5:0]

7 IRSETEN

5:0 IRSET[5:0]

Function

0: MSB first per SPI standard

1: LSB first per SPI standard

Note that the user must always change the LSB/MSB order in single-byte instructions

to avoid erratic behavior due to bit order errors

Execute software reset of SPI and controllers, reload default register values except

Register 0x00

1: Set software reset; write 0 on the next (or any following) cycle to release the reset

0: The SPI instruction word utilizes a 5-bit address

1: The SPI instruction word utilizes a 13-bit address

1: Turn core LDO voltage regulator off

0: Indicates core LDO voltage regulator is off

1: Indicates core LDO voltage regulator is on

1: Powers down all analog and digital circuitry except for SPI logic

1: Turns off Q DAC output current

1: Turns off I DAC output current

1: Turns off Q DAC clock

1: Turns off I DAC clock

1: Powers down internal voltage reference (external reference required)

0: Unsigned binary input data format

1: Twos complement input data format

0: Pairing of data—Q first of pair on data input pads

1: Pairing of data—I first of pair on data input pads (default)

0: Q data latched on DCLKIO rising edge

1: I data latched on DCLKIO falling edge (default)

0: Allows simultaneous input and output enable on DCLKIO

1: Disallows simultaneous input and output enable on DCLKIO

Controls the use of DCLKIO pad for data clock input

0: Data clock input disabled

1: Data clock input enabled (default)

Controls the use of DCLKIO pad for data clock output

0: Data clock output disabled

1: Data clock output enabled; regular strength driver

Controls the use of DCLKIO pad for data clock output

0: DCOBL data clock output disabled

1: DCOBL data clock output enabled; paralleled with DCOSGL for 2× drive current

DAC I fine gain adjustment; alters the full-scale current as shown in Figure 85

1: Enables the on-chip RSET value to be changed

Changes the value of the on-chip RSET resistor; this scales the full-scale current of the

DAC in ~0.25 dB steps (nonlinear); see Figure 84

000000: RSET = 5 kΩ

100000: RSET = 1.5 kΩ

111111: RSET = 8.5 kΩ

Rev. 0 | Page 34 of 48

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