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AD9114 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9114 Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters ADI
Analog Devices ADI
AD9114 Datasheet PDF : 48 Pages
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SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9114/AD9115/AD9116/AD9117 is a
flexible, synchronous serial communications port allowing easy
interfacing to many industry-standard microcontrollers and micro-
processors. The serial I/O is compatible with most synchronous
transfer formats, including both the Motorola SPI® and Intel®
SSR protocols. The interface allows read/write access to all
registers that configure the AD9114/AD9115/AD9116/AD9117.
Single or multiple byte transfers are supported, as well as MSB
first or LSB first transfer formats. The serial interface port of the
AD9114/ AD9115/AD9116/AD9117 is configured as a single I/O
pin on the SDIO pin.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle on the AD9114/
AD9115/AD9116/AD9117. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9114/AD9115/
AD9116/AD9117, coinciding with the first eight SCLK rising
edges. In Phase 2, the instruction byte provides the serial port
controller of the AD9114/AD9115/AD9116/AD9117 with infor-
mation regarding the data transfer cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or write,
the number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9114/AD9115/AD9116/AD9117.
A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0,
resets the SPI port timing to the initial state of the instruction
cycle. This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the midst of an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9114/
AD9115/AD9116/AD9117 and the system controller. Phase 2
of the communication cycle is a transfer of one, two, three, or
four data bytes, as determined by the instruction byte. Using
one multibyte transfer is the preferred method. Single byte
data transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
AD9114/AD9115/AD9116/AD9117
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 11.
Table 11.
MSB
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W N1 N0 A4 A3 A2 A1 A0
R/W (Bit 7 of the instruction byte) determines whether a read or a
write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 12.
Table 12. Byte Transfer Count
N1
N0
Description
0
0
Transfer 1 byte
0
1
Transfer 2 bytes
1
0
Transfer 3 bytes
1
1
Transfer 4 bytes
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte) determine which register is accessed during the
data transfer portion of the communications cycle. For multi-
byte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9114/
AD9115/AD9116/AD9117, based on the LSBFIRST bit
(Register 0x00, Bit 6).
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9114/AD9115/AD9116/AD9117 and to run the internal state
machines. The SCLK maximum frequency is 20 MHz. All data
input to the AD9114/AD9115/AD9116/AD9117 is registered on
the rising edge of SCLK. All data is driven out of the AD9114/
AD9115/AD9116/AD9117 on the falling edge of SCLK.
CS—Chip Select
An active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial commu-
nications lines. The SDIO/FORMAT pin reaches a high impedance
state when this input is high. Chip select should stay low during
the entire communication cycle.
SDIO—Serial Data I/O
The SDIO pin is used as a bidirectional data line to transmit
and receive data.
Rev. 0 | Page 31 of 48
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