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AD9114 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9114 Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters ADI
Analog Devices ADI
AD9114 Datasheet PDF : 48 Pages
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AD9114/AD9115/AD9116/AD9117
THEORY OF OPERATION
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
1.8V
LDO
SPI
INTERFACE
1V
RSET
8.5k
10k
IREF
100µA
1 INTO 2
INTERLEAVED
DATA
INTERFACE
BAND
GAP
I DATA
Q DATA
CLOCK
DIST
AD9114/AD9115/
AD9116/AD9117
RSET
8.5k
RCM
60TO
260
I DAC
AUX1DAC
AUX2DAC
Q DAC
RCM
60TO
260
62.5
62.5
62.5
62.5
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
Figure 75. Simplified Block Diagram
Figure 75 shows a simplified block diagram of the AD9114/
AD9115/AD9116/AD9117 that consists of two main DACs,
digital control logic, and a full-scale output current control. The
DAC contains a PMOS current source array capable of providing
a maximum of 20 mA. The array is divided into 31 equal currents
that make up the five most significant bits (MSBs). The next four
bits, or middle bits, consist of 15 equal current sources whose
value is 1/16 of an MSB current source. The remaining LSBs are
binary weighted fractions of the current sources of the middle
bits. Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance for
multitone or low amplitude signals and helps maintain the high
output impedance of the DAC (that is, >200 MΩ).
All of these current sources are switched to one or the other
of the two output nodes (IOUTP or IOUTN) via PMOS differential
current switches. The switches are based on the architecture
that was pioneered in the AD976x family, with further refine-
ments to reduce distortion contributed by the switching transient.
This switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9114/AD9115/AD9116/
AD9117 have separate power supply inputs (AVDD and DVDD)
that can operate independently over a 1.7 V to 3.5 V range. The
digital section, which is capable of operating at a rate of up to
125 MSPS, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.0 V band gap
voltage reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 4 mA to 20 mA via an exter-
nal resistor, RSET, connected to its full-scale adjust pin (FSADJ).
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IOUTFS, is
32 × IREF.
Optional on-chip RSET resistors are provided that can be
programmed between an nominal value of 1.5 kΩ to 8.5 kΩ
(4 mA to 20 mA IOUTFS).
The AD9114/AD9115/AD9116/AD9117 provide the option of
setting the output common mode to a value other than ACOM
via the output common-mode pin (CMLI). This facilitates directly
interfacing the output of the AD9114/AD9115/ AD9116/AD9117
to components that require common-mode levels greater than 0 V.
Rev. 0 | Page 30 of 48
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