AD9114 View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD9114 Datasheet PDF : 48 Pages
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AD9114/AD9115/AD9116/AD9117
DB9 1
DB8 2
DB7 3
DB6 4
DVDDIO 5
DVSS 6
DVDD 7
DB5 8
DB4 9
DB3 10
PIN 1
INDICATOR
AD9116
TOP VIEW
(Not to Scale)
30 RLIN
29 IOUTN
28 IOUTP
27 RLIP
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
NC = NO CONNECT
NOTES
1. THE HEAT SINK PAD IS CONNECTED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 3. AD9116 Pin Configuration
Table 8. AD9116 Pin Function Descriptions
Pin No. Mnemonic
Description
1 to 4 DB[9:6]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage (1.8 V to 3.3 V).
8 to 12 DB[5:1]
Digital Inputs.
13
DB0 (LSB)
Digital Input (LSB).
14, 15 NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level.
21
RLQN
Load Resistor (62.5 Ω) to the CMLQ Pin.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (62.5 Ω) to the CMLQ Pin.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage (1.8 V to 3.3 V).
27
RLIP
Load Resistor (62.5 Ω) to the CMLI Pin.
28
IOUTP
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
29
IOUTN
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
30
RLIN
Load Resistor (62.5 Ω) to the CMLI Pin.
31
CMLI
I DAC Output Common-Mode Level.
32
FSADJQ/AUXQ Full-Scale Current Output Adjust for Q DAC. Connect to AVSS through a resistor.
Auxiliary Q DAC Output When Internal On-Chip, RSET, is Enabled.
33
FSADJI/AUXI Full-Scale Current Output Adjust for I DAC. Connect to AVSS through a resistor.
Auxiliary I DAC Output When Internal On-Chip, RSET, is Enabled.
34
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
35
RESET/PINMD Reset. In SPI mode, pulse RESET high to reset SPI registers to default values.
Pin Mode. A constant Logic 1 puts the device into pin mode.
Rev. 0 | Page 11 of 48
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