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AD9106 View Datasheet(PDF) - Analog Devices

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AD9106 Datasheet PDF : 48 Pages
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AD9106
Stop Address3 Register (STOP_ADDR3, Address 0x56)
Table 71. Bit Descriptions for STOP_ADDR3
Bits Bit Field Name Settings Description
[15:4] STOP_ADDR3
RAM address where DAC3 stops to read waveform.
[3:0] RESERVED
Data Sheet
Reset
0x0000
0x0
Access
RWE
A
RWE
A
DDS Cycles3 Register (DDS_CYC3, Address 0x57)
Table 72. Bit Descriptions for DDS_CYC3
Bits Bit Field Name Settings Description
[15:0] DDS_CYC3
Number of sine wave cycles when DDS prestored waveform with start and
stop delays is selected for DAC3 output.
Reset
0x0001
Access
RWE
A
Start Delay2 Register (START_DLY2, Address 0x58)
Table 73. Bit Descriptions for START_DLY2
Bits Bit Field Name Settings Description
[15:0] START_DELAY2
Start delay of DAC2.
Reset Access
0x0000 RWE
A
Start Address2 Register (START_ADDR2, Address 0x59)
Table 74. Bit Descriptions for START_ADDR2
Bits Bit Field Name Settings Description
[15:4] START_ADDR2
RAM address where DAC2 starts to read waveform.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
Stop Address2 Register (STOP_ADDR2, Address 0x5A)
Table 75. Bit Descriptions for STOP_ADDR2
Bits Bit Field Name Settings Description
[15:4] STOP_ADDR2
RAM address where DAC2 stops to read waveform.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
DDS Cycle2 Register (DDS_CYC2, Address 0x5B)
Table 76. Bit Descriptions for DDS_CYC2
Bits Bit Field Name Settings Description
[15:0] DDS_CYC2
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC2 output.
Reset
0x0001
Access
RWE
A
Start Delay1 Register (START_DLY1, Address 0x5C)
Table 77. Bit Descriptions for START_DLY1
Bits Bit Field Name Settings Description
[15:0] START_DELAY1
Start delay of DAC1.
Reset
0x0000
Access
RWE
A
Rev. A | Page 46 of 48
 

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