AD9106 View Datasheet(PDF) - Analog Devices
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AD9106 Datasheet PDF : 48 Pages
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Data Sheet
AD9106
Trigger Start to DOUT Signal Register (DOUT_START_DLY, Address 0x2C)
Table 44. Bit Descriptions for DOUT_START_DLY
Bits Bit Field Name
Settings Description
[15:0] DOUT_START
Time between trigger low and DOUT signal high in number of DAC
clock cycles.
Reset Access
0x0003 RWE
A
DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)
Table 45. Bit Descriptions for DOUT_CONFIG
Bits Bit Field Name Settings Description
[15:6] RESERVED
5
DOUT_VAL
Manually sets DOUT signal value, only valid when DOUT_MODE = 0
(manual mode).
4
DOUT_MODE
Sets different enable signal mode.
0x0
DOUT pin is output from SDO/SDI2/DOUT pin and is manually controlled
by Bit 5, DOUT_EN in Register 0x00 which must be set to use this feature.
0x1
DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by
DOUT_START and DOUT_STOP. DOUT_EN in Register 0x00 must be set to
use this feature.
[3:0] DOUT_STOP
Time between pattern end and DOUT signal low in number of DAC clock
cycles.
Reset
0x0000
0
Access
RWE
A
RWE
A
0
RWE
A
0x0
RWE
A
DAC4 Constant Value Register (DAC4_CST, Address 0x2E)
Table 46. Bit Descriptions for DAC4_CST
Bits Bit Field Name Settings Description
[15:4] DAC4_CONST
Most significant byte of DAC4 constant value.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
DAC3 Constant Value Register (DAC3_CST, Address 0x2F)
Table 47. Bit Descriptions for DAC3_CST
Bits Bit Field Name Settings Description
[15:4] DAC3_CONST
Most significant byte of DAC3 constant value.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
DAC2 Constant Value Register (DAC2_CST, Address 0x30)
Table 48. Bit Descriptions for DAC2_CST
Bits Bit Field Name Settings Description
[15:4] DAC2_CONST
Most significant byte of DAC2 constant value.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
DAC1 Constant Value Register (DAC1_CST, Address 0x31)
Table 49. Bit Descriptions for DAC1_CST
Bits Bit Field Name Settings Description
[15:4] DAC1_CONST
Most significant byte of DAC1 constant value.
[3:0] RESERVED
Reset
0x000
0x0
Access
RWE
A
RWE
A
Rev. A | Page 41 of 48
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