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AD9106BCPZ View Datasheet(PDF) - Analog Devices

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Description
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AD9106BCPZ Datasheet PDF : 48 Pages
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AD9106
Data Sheet
Bits Bit Field Name Settings Description
Reset Access
[5:4] PRESTORE_SEL1
0x0
RWE
A
0
Constant value held into DAC1 constant value MSB/LSB register.
1
Sawtooth defined in DAC1 sawtooth configuration register
(SAW2_1CONFIG).
2
Pseudo-random sequence.
3
DDS1 output.
3
MASK_DAC3
Mask DAC3 to DAC3_CONST value.
0
RWE
A
2
CH1_ADD
Add DAC1 and DAC3, output at DAC1.
0
RWE
A
0
Normal operation for DAC1/DAC3.
1
Add DAC1 and DAC3, and output at DAC1. In this start_delay case, DAC3
output remains unchanged.
[1:0] WAVE_SEL1
0x1
RWE
A
0
Waveform read from RAM between START_ADDR1 and STOP_ADDR1.
1
Prestored waveform.
2
Prestored waveform using START_DELAY1 and PATTERN_PERIOD.
3
Prestored waveform modulated by waveform from RAM.
DAC Time Control Register (PAT_TIMEBASE, Address 0x28)
Table 40. Bit Descriptions for PAT_TIMEBASE
Bits Bit Field Name
Settings Description
[15:12] RESERVED
[11:8] HOLD
Number of times the DAC value holds the sample (0 = DAC holds for 1
sample).
[7:4] PAT_PERIOD_BASE
Number of DAC clock period per PATTERN_PERIOD LSB
(0 = PATTERN_PERIOD LSB = 1 DAC clock period).
[3:0] START_DELAY_BASE
Number of DAC clock period per START_DELAYx LSB
(0 = START_DELAYx LSB = 1 DAC clock period).
Reset
0x00
0x1
0x1
0x1
Access
RWE
A
RWE
A
RWE
A
RWE
A
Pattern Period Register (PAT_PERIOD, Address 0x029)
Table 41. Bit Descriptions for PAT_PERIOD
Bits Bit Field Name Settings Description
[15:0] PATTERN_PERIOD
Pattern period register.
Reset Access
0x8000 RWE
A
DAC3/DAC4 Pattern Repeat Cycles Register (DAC4_3PATx, Address 0x2A)
Table 42. Bit Descriptions for DAC4_3PATx
Bits Bit Field Name
Settings Description
[15:8] DAC4_REPEAT_CYCLE
Number of DAC4 pattern repeat cycles + 1, (0 repeat 1 pattern).
[7:0] DAC3_REPEAT_CYCLE
Number of DAC3 pattern repeat cycles + 1, (0 repeat 1 pattern).
Reset
0x01
0x01
Access
RWE
A
RWE
A
DAC1/DAC2 Pattern Repeat Cycles Register (DAC2_1PATx, Address 0x2B)
Table 43. Bit Descriptions for DAC2_1PATx
Bits Bit Field Name
Settings Description
[15:8] DAC2_REPEAT_CYCLE
Number of DAC2 pattern repeat cycles + 1, (0 repeat 1 pattern).
[7:0] DAC1_REPEAT_CYCLE
Number of DAC1 pattern repeat cycles + 1, (0 repeat 1 pattern).
Reset
0x01
0x01
Access
RWE
A
RWE
A
Rev. A | Page 40 of 48
 

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