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AD9106BCPZ View Datasheet(PDF) - Analog Devices

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AD9106BCPZ Datasheet PDF : 48 Pages
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Data Sheet
Figure 52 shows all DACx outputting sine waves modulated by
an amplitude envelope. The sine wave is generated by the DDS
and the amplitude envelope is stored in SRAM. Different start
delays and digital gain multipliers are applied by each DACx
input data path.
PATTERN_PERIOD
START_DLY1
DAC1
DATA @
START_ADDR1
START_DLY2
DAC2
DATA @
START_ADDR2
START_DLY3
DATA @
STOP_ADDR1
DATA @
STOP_ADDR2
DAC3
DATA @
START_ADDR3
DATA @
STOP_ADDR3
START_DLY4
DAC4
DATA @
START_ADDR4
DATA @
STOP_ADDR4
Figure 52. DDS Output Amplitude Modulated by RAM Envelope
Figure 53 and Figure 54 show the four DACs generating
continuous waveforms. One with start delays, one without.
START_DLY1
DAC1
START_DLY2
DAC2
START_DLY3
DAC3
AD9106
DAC4
START_DLY4
Figure 53. Waveforms with Start Delays
DAC1
DAC2
DAC3
DAC4
Figure 54. Waveforms Without Start Delays
Rev. A | Page 29 of 48
 

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