AD9106BCPZ View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

AD9106BCPZ

Quad, Low Power, 12-Bit, 180 MSPS, Digital-toAnalog Converter and Waveform Generator

Analog Devices 

AD9106

APPLICATIONS INFORMATION

SIGNAL GENERATION EXAMPLES

AD9106 waveform and pattern generation examples are

provided in this section.

Figure 49 shows a different waveform being generated by each

DACx. The waveforms are all stored in the 4K × 12 SRAM in

different segments. DACx path address counters access the

SRAM simultaneously. Each waveform is repeated once during

each pattern period. In each pattern period a start delay is

executed, then the pattern is read from SRAM.

TRIGGER

PATTERN

EXECUTED

PATTERN

EXECUTED

PATTERN_PERIOD

START_DLY1

DAC1

START_DLY2

DAC2

START_DLY3

DATA @

START_ADDR1

DATA @

STOP_ADDR1

DATA @

START_ADDR2

DATA @

STOP_ADDR2

PATTERN

EXECUTED

DAC3

START_DLY4

DATA @

START_ADDR3

DATA @

STOP_ADDR3

DAC4

DATA @

START_ADDR4

DATA @

STOP_ADDR4

Figure 49. Pattern Using Different Waveforms Stored in SRAM

Figure 50 shows pulsed sine waves generated by each DACx.

The DDS generates a sine wave at a programmed frequency.

Each DACx channel is programmed with a start delay and a

number of sine wave cycles to output.

Data Sheet

PATTERN_PERIOD

START_DLY1 #CYCLES1

DAC1

START_DLY2 #CYCLES2

DAC2

#CYCLES3

START_DLY3

DAC3

#CYCLES4

START_DLY4

DAC4

Figure 50. Pulsed Sine Waves in Pattern Periods

Figure 51 shows a pulsed sinewave generated by DAC1 and each

of the three available sawtooth wave shapes generated by DAC2,

DAC3, and DAC4 in successive pattern periods with start delay.

PATTERN_PERIOD

START_DLY1 #CYCLES1

DAC1

START_DLY2

DAC2

START_DLY3

DAC3

START_DLY4

DAC4

Figure 51. Pulsed SineWaves and Sawtooth Waveforms in Pattern Periods

Rev. A | Page 28 of 48

Share Link: