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AD9106 View Datasheet(PDF) - Analog Devices

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AD9106 Datasheet PDF : 48 Pages
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AD9106
Data Sheet
DACx Digital Gain Multiplier
On its way into each DACx, the samples are multiplied by a
12-bit gain factor that has a range of ±2.0. These gain values are
programmed in the DACx_DGAIN registers.
DACx Digital Offset Summer
DACx input samples are summed with a 12-bit dc offset
value as well. The dc offset values are programmed in the
DACxDOF registers.
DACx Waveform Selectors
Waveform selector inputs are
DACx sawtooth generator output
DACx pseudo random sequence generator output
DACx dc constant generator output
DACx pulsed, phase shifted DDS sine wave output
RAM output
DACx pulsed, phase shifted DDS sine wave output
amplitude modulated by ram output
Waveform selection for each DACx is made by programming
the WAVEx_yCONFIG registers.
DACx Pattern Period Repeat Controller
The PATTERN_RPT bit in the PAT_TYPE register controls
whether the pattern output auto repeats (periodic pulse train
repeats indefinitely) or repeats a number of consecutive times
defined by the DACx_REPEAT_CYCLE fields. The latter are
periodic pulse trains that repeat a finite number of times.
DACx, Number of DDS Cycles
Each DACx input data path establishes the pulse width of the
sine wave output from the single common DDS in number
of sine wave cycles. The cycle counts are programmed in
DDS_CYCx registers.
DACx DDS Phase Shift
Each DACx input data path shifts the phase of the output of the
single common DDS. The phase shift is programmed using the
DDSx_PHASE fields.
DOUT FUNCTION
In applications where AD9106 DACs drive high voltage
amplifiers, such as in ultrasound transducer array element
driver signal chains, it can be useful to turn on and off each
amplifier at precise times relative to the waveform generated by
each AD9106 DAC. The SDO/SDI2/DOUT terminal, can be
configured to provide this function. One amplifier on/off strobe
can be provided for all four DACs.
The SPI interface needs to be configured in 3-wire mode (see
Figure 32 and Figure 33). This is accomplished by setting the
SPI3WIRE or SPI3WIREM bits in the SPICONFIG register.
When SPID_RV or SPI_DRVM of the SPICONFIG register is
set to Logic 1, the SDO/SDI2/DOUT terminal provides the
DOUT function.
Manually Controlled DOUT
If DOUT_MODE = 0 in the DOUT_CONFIG register, DOUT can
be turned on or off using the DOUT_VAL bit of that same register.
Pattern Generator Controlled DOUT
Figure 46 depicts the rising edge of a pattern generator
controlled DOUT pulse. Figure 47 shows the falling edge.
Pattern generator controlled DOUT is set by setting
DOUT_MODE = 1. Then, the start delay is programmed in the
DOUT_START_DLY register and the stop delay is programmed
into the DOUT_STOP field of the DOUT_CONFIG register.
DOUT goes high DOUT_START[15:0] CLKP/CLKN cycles
after the falling edge of the signal input to the trigger terminal.
DOUT stays high as long as a pattern is being generated. DOUT
goes low DOUT_STOP[3:0] CLKP/CLKN cycles after the clock
edge that causes pattern generation to stop.
DOUT DELAY=
DOUT_START[15:0] CLKP/CLKN CYCLES
tSU
TRIGGER
CLKP/
CLKN
DOUT
Figure 46. DOUT Start Sequence
PATTERN
STOPS
PATTERN
GENERATOR
STATE
CLKP/CLKN
PATTERN ON
PATTERN OFF
DOUT DELAY = DOUT_STOP[3:0]
CLKP/CLKN CYCLES
DOUT
Figure 47. DOUT Stop Sequence
DIRECT DIGITAL SYNTHESIZER (DDS)
The direct digital synthesizer generates a sine wave that can be
output on any of the four DACx. The DDS is a global shared
signal resource. It can generate one sinusoid at a frequency
determined by its tuning word input. The tuning word is 24 bits
wide. The resolution of DDS tuning is FCLKP/CLKN/224. The DDS
output frequency is DDS_TW × FCLKP/CLKN/224.
The DDS tuning word is programmed using one of two
methods. For a fixed frequency, DDSTW_MSB and
DDSTW_LSB are programmed with a constant. When the
frequency of the DDS needs to change within each pattern
period, a sequence of values stored in SRAM is combined with
a selection of DDSTW_MSB bits to form the tuning word.
Rev. A | Page 26 of 48
 

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