AD9106 View Datasheet(PDF) - Analog Devices

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AD9106

Quad, Low Power, 12-Bit, 180 MSPS, Digital-toAnalog Converter and Waveform Generator

Analog Devices 

Data Sheet

Pattern Types

• Continuous waveforms are output by some or all DACx for

the duration of the pattern on state of the pattern

generator. Continuous waveforms ignore pattern periods.

• Periodic pulse trains that repeat indefinitely are waveforms

that are output once during each pattern period. Pattern

periods occur one after the other as long as the pattern

generator is in the pattern on state.

• Periodic pulse trains that repeat a finite number of times

are just like those that repeat indefinitely except that the

waveforms are output during a finite number of

consecutive pattern periods.

TRIGGER

PATTERN

EXECUTED

PATTERN

EXECUTED

PATTERN_PERIOD

START_DLY1

DAC1

START_DLY2

DAC2

START_DLY3

DATA @

START_ADDR.1

DATA @

STOP_ADDR.1

DATA @

START_ADDR.2

DATA @

STOP_ADDR.2

PATTERN

EXECUTED

DAC3

START_DLY4

DATA @

START_ADDR.3

DATA @

STOP_ADDR.3

DAC4

DATA @

START_ADDR.4

DATA @

STOP_ADDR.4

Figure 42. Periodic Pulse Trains output on all DACx

PATTERN GENERATOR PROGRAMMING

Figure 44 shows periodic pulse train waveforms as seen at

the output to each of the four DACx. The four waveforms are

generated in each pattern period. Each has its own start delay

(START_DLYx), a delay between the start of each pattern

period and the start of the waveform. The four DACx

waveforms are the same digital signal stored in SRAM and

multiplied by the DACx digital gain factor. The SRAM data

is read using each DACx address counter simultaneously.

Setting Pattern Period

Two register bit fields are used to set the pattern period. The

PAT_PERIOD_BASE field in the PAT_TIMEBASE register sets

the number of CLKP/N clock per PATTERN_PERIOD LSB.

The PATTERN_PERIOD is programmed in the PAT_PERIOD

register. The longest pattern period available is 65535 ×

16/FCLKP/CLKN.

AD9106

Setting Waveform Start Delay Base

The waveform start delay base is programmed in the

START_DELAY_BASE field of the PAT_TIMEBASE register.

Each DACx has a START_DLYx register described in

the DACX Input Data Paths section. The start delay base

determines how many CLKP/CLKN clock cycles there are

per START_DELAYx LSB.

RUN BIT

TRIGGER

tDLY = PATTERN_DELAY VALUE + 1

tSU

PATTERN

STARTS

CLKP/

CLKN

PATTERN

GENERATOR

STATE

PATTERN

GENERTAOR OFF

PATTERN

GENERTAOR ON

Figure 43. Trigger Initiated Pattern Start with Pattern Delay

tSU

TRIGGER

CLKP/

CLKN

PATTERN

GENERATOR

STATE

PATTERN ON

PATTERN OFF

PATTERN

STOPS

Figure 44. Trigger Rising Edge Initiated Pattern Stop

RUN

BIT

CLKP/

CLKN

PATTERN

GENERATOR

STATE

PATTERN ON

PATTERN OFF

PATTERN

STOPS

Figure 45. RUN Bit Driven Pattern Stop

DACx INPUT DATA PATHS

Each of the four DACx has its own digital data path. Timing

in the DACx data paths is governed by the pattern generator.

Each DACx data path includes a waveform selector, a waveform

repeat controller, RAM output and DDS output multiplier

(RAM output can amplitude modulate DDS output), DDSx

cycle counter, DACx digital gain multiplier, and a DACx digital

offset summer.

Rev. A | Page 25 of 48

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