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AD9106 View Datasheet(PDF) - Analog Devices

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AD9106 Datasheet PDF : 48 Pages
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AD9106
CLK+
CLK–
50Ω*
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
LVDS DRIVER
0.1µF
CLK
50Ω*
100Ω
0.1µF
CLKP
AD9106
CLKN
*50Ω RESISTORS ARE OPTIONAL.
Figure 38. Differential LVDS Clock Input
In applications where the analog output signals are at low
frequencies, it is acceptable to drive the AD9106 clock input
with a single-ended CMOS signal. Figure 39 shows such an
interface. CLKP is driven directly from a CMOS gate, and the
CLKN pin is bypassed to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor. The optional resistor is a series
termination.
CLK+
0.1µF
50Ω
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
CLKP
AD9106
0.1µF
CLKN
39kΩ
CLK+
CLK–
50Ω*
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
0.1µF
CLKP
PECL DRIVER
0.1µF
CLK
50Ω*
240
100
0.1µF
240
AD9106
CLKN
*50Ω RESISTORS ARE OPTIONAL.
Figure 40. Differential PECL Sample Clock
CLK+
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
50Ω
0.1µF
SCHOTTKY
DIODES:
HSM2812
Figure 41. Transformer Coupled Clock
CLKP
AD9106
CLKN
DAC OUTPUT CLOCK EDGE
Each of the four DACs can be configured independently to
output samples on the rising or falling edge of the CLKP/CLKN
clock input by configuring the DACx_INV_CLK bits in the
CLOCKCONFIG register. This functionality sets the DAC
output timing resolution at 1/(2 × FCLKP/CLKN).
Data Sheet
GENERATING SIGNAL PATTERNS
The AD9106 can generate three types of signal patterns under
control of its programmable pattern generator.
Continuous waveforms
Periodic pulse train waveforms that repeat indefinitely
Periodic pulse train waveforms that repeat a finite number
of times
Run Bit
Setting the RUN bit in the PAT_STATUS register to 1 arms the
AD9106 for pattern generation. Clearing this bit shuts down the
pattern generator as shown in Figure 45.
Trigger Terminal
A falling edge on the trigger terminal starts the generation of a
pattern. If RUN is set, the falling edge of trigger starts pattern
generation. As shown in Figure 43, the pattern generator state
goes to “pattern on” a number of CLKP/CLKN clock cycles
following the falling edge of trigger. This delay is programmed
in the PATTERN_DELAY bit field.
The rising edge on the trigger terminal is a request for the
termination of pattern generation (see Figure 44).
Pattern Bit (Read Only)
The read-only PATTERN bit in the PAT_STATUS register
indicates, when set to 1, that the pattern generator is in the
“pattern on” state. A 0 indicates that the pattern generator is in
the “pattern off ” state.
Rev. A | Page 24 of 48
 

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