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AD9106BCPZ View Datasheet(PDF) - Analog Devices

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AD9106BCPZ Datasheet PDF : 48 Pages
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AD9106
Writing to On-Chip SRAM
The AD9106 includes an internal 4096 × 12 SRAM. The SRAM
address space is 0x6000 to 0x6FFF of the AD9106 SPI address map.
Double SPI for Write for SRAM
The time to write data to the entire SRAM can be halved using
the SPI access mode shown in Figure 35. The SDO/SDI2/
DOUT line becomes a second serial data input line, doubling
the achievable update rate of the on-chip SRAM. SDO/SDI2/
DOUT is write-only in this mode. The entire SRAM can be
written in (2 + 2 × 4096) × 8/(2 × FSCLK) seconds.
SET WAVEFORM ADDRESS
CS
TO BE READ/WRITTEN
WAVEFORM DATA TO BE WRITTEN
SCLK
SDIO
SDO/
SDI2/
DOUT
WAVEFORM PATTERN
ADDRESS1 = N
WAVEFORM
PATTERN DATA
WAVEFORM PATTERN
ADDRESS2 = M
WAVEFORM
PATTERN DATA
Figure 35. Double SPI Write of SRAM Data
Configuration Register Update Procedure
Most SPI accessible registers are double buffered. An active
register set controls operation of the AD9106 during pattern
generation. A set of shadow registers stores updated register
values. Register updates can be written at any time and when
the configuration update is complete, a 1 is written to the
UPDATE bit in the RAMUPDATE register. The UPDATE bit
arms the register set for transfer from shadow registers to active
registers. The AD9106 will perform this transfer automatically
the next time the pattern generator is off. This procedure does
not apply to the 4K × 12 SRAM. Refer to the SRAM section for
the SRAM update procedure.
DAC TRANSFER FUNCTION
The AD9106 DACs provide four differential current outputs:
IOUTP1/IOUTN1, IOUTP2/IOUTN2, IOUTP3/IOUTN3, and
IOUTP4/IOUTN4.
The DAC output current equations are as follows:
IOUTPx= IOUTFSx × xDAC INPUT CODE/212
(1)
IOUTNx = IOUTFSx × ((212 − 1) − xDAC INPUT CODE)/212
(2)
where:
xDAC INPUT CODE = 0 to 212 − 1.
IOUTFSx = full-scale current or DAC gain set independently for
each DAC.
Data Sheet
IOUTFSx = 32 × IIREFx
(3)
where:
IREFx = VREFIO/xRSET
(4)
IREFx is the current that flows through each IREFx resistor. Each
DAC has its own IREF set resistor. IREF resistors may be on or off
chip at the users’ discretion. When on-chip xRSET resistors are
in use, DAC gain accuracy can be improved by employing the
product’s built in automatic gain calibration capability.
ANALOG CURRENT OUTPUTS
Optimum linearity and noise performance of DAC outputs
can be achieved when they are connected differentially to an
amplifier or a transformer. In these configurations, common-
mode signals at the DAC outputs are rejected.
The output compliance voltage specifications shown in
Table 1 and Table 2 must be adhered to for the performance
specifications in these tables to be met.
SETTING IOUTFSx, DAC GAIN
As expressed in Equation 3 and Equation 4, DAC gain (IOUTFSx)
is a function of the reference voltage at the REFIO terminal and
xRSET for each DAC.
Voltage Reference
The AD9106 contains an internal 1.0 V nominal band gap
reference. The internal reference may be used. Alternatively,
it can be replaced by a more accurate off-chip reference. An
external reference can provide tighter reference voltage
tolerances and/or lower temperature drift than the on-chip
band gap.
By default, the on-chip reference is powered up and ready to be
used. When using the on-chip reference, the REFIO terminal
needs to be decoupled to AGND using a 0.1 μF capacitor as
shown in Figure 36.
AD9106
VBG
1.0V
DACx
REFIO
+
0.1µF
FSADJx
xRSET
CURRENT
SCALING
x32
IOUTFSx
AVSS
IREFx
Figure 36. On-Chip Reference with External xRSET Resistor
Table 13 summarizes reference connections and programming.
Table 13. Reference Operation
Reference Mode
REFIO Pin
Internal
Connect 0.1 µF capacitor
External
Connect off-chip reference
Rev. A | Page 22 of 48
 

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